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Resource Contention in Real-time Systems
The divide—and—conquer method is extensively used for system design. For real-time systems the separated components execute concurrently using some common computational infrastructure and this can lead to contention for system resources, such as processors, memory, communication channels, and so on. Unless the resource contention is accommodated, then a system built from the composition of components may not function as expected and the “proven” behaviour of the components can be invalid. To overcome this uncertainty a divide—conquer—and—system-composition method is required. This thesis takes a different approach to many of the existing notations which focus on descriptions of behaviour. The Composite Transition System notation and algebra presented here enables the resource usage of the components to be specified and combined to form a composite system of concurrently executing components. By relating the composite system to the realisable behaviour of the system resources provided by the common infrastructure it becomes possible to determine any violation of the constraints imposed by the system resources. If the composite system model is then constrained by the resource behaviours then it is possible through an extraction operation to determine the modified behaviour of the components that will yield a system free of resource contention. Component specification, concurrent composition, the application of system level constraints and extraction are applied in this thesis to a system encountered in a commercial application. The purpose of this example is to demonstrate contention modelling and the mathematics of the notation, rather than to prove any specific properties of the application. Deployment of the notation to more complex applications will require the development of software tools to compute concurrent composition and extraction, and this is the motivation for the mathematical treatment in this thesis
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This PhD dissertation has resulted in six
publications in which one of the papers received Best Paper
Award at ICESS 2021. All the papers were published in
reputed venues for real-time systems research, i.e., RTSS
2020, RTNS 2021, ICESS 2021, RTCSA 2022, RTSS 2022,
Elsevier’s Journal of System Architecture. Two more papers
are expected to be published soon.Multicore platforms share the hardware resources such as caches, interconnects, and main memory among all the cores. Due to such sharing, tasks running on different cores compete to access these shared resources which can potentially result in shared resource contention. This shared resource contention can increase the execution times of tasks in a non-deterministic manner. Consequently, the shared resource contention is problematic for hard real-time systems, i.e., systems that run tasks with stringent timing requirements. To address this issue, this PhD dissertation builds novel solutions to model and analyze the shared resource contention that can be suffered by tasks executing on a multicore system. The shared resource contention aware schedulability analysis is then derived by integrating the maximum shared resource contention that can be suffered by the tasks.This work was supported by the CISTER Research
Unit (UIDP/UIDB/04234/2020), financed by National Funds
through FCT/MCTES (Portuguese Foundation for Science and
Technology); by project ADACORSA (ECSEL/0010/2019 -
JU grant nr. 876019) financed through National Funds from
FCT and European funds through the EU ECSEL JU. The JU
receives support from the European Union’s Horizon 2020 research and innovation programme and Austria, Sweden, Spain,
Italy, France, Portugal, Ireland, Finland, Slovenia, Poland,
Netherlands, Turkey - Disclaimer: This document reflects only
the author’s view and the Commission is not responsible for
any use that may be made of the information it contains. This
work is also a result of the work developed under project
Aero.Next Portugal (nÂş C645727867-00000066) and FLY-PT
(grant nÂş 46079, POCI-01-0247-FEDER-046079), also funded
by FCT under PhD grant 2020.09532.BD.info:eu-repo/semantics/publishedVersio
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The use of Petri nets for modeling pipelined processors
This paper discusses the use of Petri Nets for modeling and analyzing pipelined processors. Petri Nets are particularly well-suited to modeling the synchronization, buffering, resource contention and delicate timing so common in pipelined processors. Tools for simulating, animating and analyzing the behavior of the models are described. The usefulness of the tools and the analysis methods they support in evaluating the performance and analyzing the detailed timing of pipelined microprocessors is illustrated through an example
DeepPicar: A Low-cost Deep Neural Network-based Autonomous Car
We present DeepPicar, a low-cost deep neural network based autonomous car
platform. DeepPicar is a small scale replication of a real self-driving car
called DAVE-2 by NVIDIA. DAVE-2 uses a deep convolutional neural network (CNN),
which takes images from a front-facing camera as input and produces car
steering angles as output. DeepPicar uses the same network architecture---9
layers, 27 million connections and 250K parameters---and can drive itself in
real-time using a web camera and a Raspberry Pi 3 quad-core platform. Using
DeepPicar, we analyze the Pi 3's computing capabilities to support end-to-end
deep learning based real-time control of autonomous vehicles. We also
systematically compare other contemporary embedded computing platforms using
the DeepPicar's CNN-based real-time control workload. We find that all tested
platforms, including the Pi 3, are capable of supporting the CNN-based
real-time control, from 20 Hz up to 100 Hz, depending on hardware platform.
However, we find that shared resource contention remains an important issue
that must be considered in applying CNN models on shared memory based embedded
computing platforms; we observe up to 11.6X execution time increase in the CNN
based control loop due to shared resource contention. To protect the CNN
workload, we also evaluate state-of-the-art cache partitioning and memory
bandwidth throttling techniques on the Pi 3. We find that cache partitioning is
ineffective, while memory bandwidth throttling is an effective solution.Comment: To be published as a conference paper at RTCSA 201
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