Stabilization of multiple resistance levels by current-sweep in SiOx-based resistive switching memory

Using current-sweep measurements, the set process in SiOx-based resistive random access memory (RRAM) has been found to consist of multiple resistance-reduction steps. Variation in set behaviors was observed and attributed to different defect distributions in the resistance switching region. Physical mechanism of electroforming process is discussed, which further explains the observed variation of defect distributions. A compliance current study confirms that the achievable memory states of SiOx RRAM are determined by its set behavior. This finding provides additional insight on achieving multi-bit memory storage with SiOx RRAM. (C) 2015 AIP Publishing LLC.Microelectronics Research Cente

Advanced physical modeling of SiOx resistive random access memories

We apply a three-dimensional (3D) physical simulator, coupling self-consistently stochastic kinetic Monte Carlo descriptions of ion and electron transport, to investigate switching in silicon-rich silica (SiOx) redox-based resistive random-access memory (RRAM) devices. We explain the intrinsic nature of resistance switching of the SiOx layer, and demonstrate the impact of self-heating effects and the initial vacancy distributions on switching. We also highlight the necessity of using 3D physical modelling to predict correctly the switching behavior. The simulation framework is useful for exploring the little-known physics of SiOx RRAMs and RRAM devices in general. This proves useful in achieving efficient device and circuit designs, in terms of performance, variability and reliability

New technology may help scale up memory storage capacity

Silicon-based memory devices such as hard drives and flash drives are in high demand for gadgets that require storage. Conventional semiconductor material-based memory devices have limited scale-up ability to increase their storage capacity. Hence, there is a quest in developing new memory technologies with superior characteristics. In this direction, a group of Indian researchers has developed a new type of resistive random access memory (RRAM) device that can be controlled with magnetic fields

Discussion On Device Structures And Hermetic Encapsulation For SiOx Random Access Memory Operation In Air

An edge-free structure and hermetic encapsulation technique are presented that enable SiOx-based resistive random-access memory (RRAM) operation in air. A controlled etch study indicates that the switching filament is close to the SiOx surface in devices with an exposed SiOx edge. Electrical test of encapsulated, edge-free devices in 1 atmosphere air indicates stable switching characteristics, unlike devices with an edge. This work demonstrates that SiOx RRAM is able to operate in air with proper encapsulation and an edge-free structure. The resistive switching failure mechanism when operating in air is explained by the oxidation of hydrogen-complexed defects in the switching filament. (C) 2014 AIP Publishing LLC.National Science Foundation IIP-1127537Microelectronics Research Cente

In-Line-Test of Variability and Bit-Error-Rate of HfOx-Based Resistive Memory

Spatial and temporal variability of HfOx-based resistive random access memory (RRAM) are investigated for manufacturing and product designs. Manufacturing variability is characterized at different levels including lots, wafers, and chips. Bit-error-rate (BER) is proposed as a holistic parameter for the write cycle resistance statistics. Using the electrical in-line-test cycle data, a method is developed to derive BERs as functions of the design margin, to provide guidance for technology evaluation and product design. The proposed BER calculation can also be used in the off-line bench test and build-in-self-test (BIST) for adaptive error correction and for the other types of random access memories.Comment: 4 pages. Memory Workshop (IMW), 2015 IEEE Internationa

The Efficacy of Programming Energy Controlled Switching in Resistive Random Access Memory (RRAM)

Current state-of-the-art memory technologies such as FLASH, Static Random Access Memory (SRAM) and Dynamic RAM (DRAM) are based on charge storage. The semiconductor industry has relied on cell miniaturization to increase the performance and density of memory technology, while simultaneously decreasing the cost per bit. However, this approach is not sustainable because the charge-storage mechanism is reaching a fundamental scaling limit. Although stack engineering and 3D integration solutions can delay this limit, alternate strategies based on non-charge storage mechanisms for memory have been introduced and are being actively pursued. Resistive Random Access Memory (RRAM) has emerged as one of the leading candidates for future high density non-volatile memory. The superior scalability of RRAMs is based on the highly localized active switching region and filamentary conductive path. Coupled with its simple structure and compatibility with complementary metal oxide semiconductor (CMOS) processes; RRAM cells have demonstrated switching performance comparable to volatile memory technologies such as DRAMs and SRAMs. However, there are two serious barriers to RRAM commercialization. The first is the variability of the resistance state which is associated with the inherent randomness of the resistive switching mechanism. The second is the filamentary nature of the conductive path which makes it susceptible to noise. In this experimental thesis, a novel program-verify (P-V) technique was developed with the objective to specifically address the programming errors and to provide solutions to the most challenging issues associated with these intrinsic failures in current RRAM technology. The technique, called Compliance-free Ultra-short Smart Pulse Programming (CUSPP), utilizes sub-nanosecond pulses in a compliance-free setup to minimize the programming energy delivered per pulse. In order to demonstrate CUSPP, a custom-built picosecond pulse generator and feedback control circuit was designed. We achieved high (108 cycles) endurance with state verification for each cycle and established high-speed performance, such as 100 ps write/erase speed and 500 kHz cycling rate of HfO2-based RRAM cells. We also investigate switching failure and the short-term instability of the RRAM using CUSPP