Improving the Power Electronics Laboratory teaching/learning process: an interactive web tool

European Higher Education Area; Power Electronics Laboratory; educational methods Resumen: The forthcoming European Higher Education Area implies an important change in the teaching/learning process: it is necessary to get students more involved as well as to promote their independence and active participation. To achieve this objective, the new teaching methodologies aimed at more effective and appropriate learning for professional practice involve the use of audiovisual, computer and multimedia tools on the part of lecturers. Therefore, a web tool, based on a content management system, has been developed for the teaching in Power Electronics Laboratory. Moreover, the use of these multimedia tools makes possible to promote the students independence. Finally, the use of this web tool results in a very significant increase in the motivation students.Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech

Financial Analysis of a Grid-connected Photovoltaic System in South Florida

In this paper the performance and financial analysis of a grid-connected photovoltaic system installed at Florida Atlantic University (FAU) is evaluated. The power plant has the capacity of 14.8 kW and has been under operation since August 2014. This solar PV system is composed of two 7.4 kW sub-arrays, one fixed and one with single axis tracking. First, an overview of the system followed by local weather characteristics in Boca Raton, Florida is presented. In addition, monthly averaged daily solar radiation in Boca Raton as well as system AC are calculated utilizing the PVwatts simulation calculator. Inputs such as module and inverter specifications are applied to the System Advisor Model (SAM) to design and optimize the system. Finally, the estimated local load demand as well as simulation results are extracted and analyzed.Comment: 6 Pages, IEEE PVSC 2017 Conference, Washington D.

MISSED: an environment for mixed-signal microsystem testing and diagnosis

A tight link between design and test data is proposed for speeding up test-pattern generation and diagnosis during mixed-signal prototype verification. Test requirements are already incorporated at the behavioral level and specified with increased detail at lower hierarchical levels. A strict distinction between generic routines and implementation data makes reuse of software possible. A testability-analysis tool and test and DFT libraries support the designer to guarantee testability. Hierarchical backtrace procedures in combination with an expert system and fault libraries assist the designer during mixed-signal chip debuggin

Functional Verification of Power Electronic Systems

This project is the final work of the degree in Industrial Electronics and Automatic Engineering. It has global concepts of electronics but it focuses in power electronic systems. There is a need for reliable testing systems to ensure the good functionality of power electronic systems. The constant evolution of this products requires the development of new testing techniques. This project aims to develop a new testing system to accomplish the functional verification of a new power electronic system manufactured on a company that is in the power electronic sector . This test system consists on two test bed platforms, one to test the control part of the systems and the other one to test their functionality. A software to perform the test is also designed. Finally, the testing protocol is presented. This design is validated and then implemented on a buck converter and an inverter that are manufactured at the company. The results show that the test system is reliable and is capable of testing the functional verification of the two power electronic system successfully. In summary, this design can be introduced in the power electronic production process to test the two products ensuring their reliability in the market

Verified AIG Algorithms in ACL2

And-Inverter Graphs (AIGs) are a popular way to represent Boolean functions (like circuits). AIG simplification algorithms can dramatically reduce an AIG, and play an important role in modern hardware verification tools like equivalence checkers. In practice, these tricky algorithms are implemented with optimized C or C++ routines with no guarantee of correctness. Meanwhile, many interactive theorem provers can now employ SAT or SMT solvers to automatically solve finite goals, but no theorem prover makes use of these advanced, AIG-based approaches. We have developed two ways to represent AIGs within the ACL2 theorem prover. One representation, Hons-AIGs, is especially convenient to use and reason about. The other, Aignet, is the opposite; it is styled after modern AIG packages and allows for efficient algorithms. We have implemented functions for converting between these representations, random vector simulation, conversion to CNF, etc., and developed reasoning strategies for verifying these algorithms. Aside from these contributions towards verifying AIG algorithms, this work has an immediate, practical benefit for ACL2 users who are using GL to bit-blast finite ACL2 theorems: they can now optionally trust an off-the-shelf SAT solver to carry out the proof, instead of using the built-in BDD package. Looking to the future, it is a first step toward implementing verified AIG simplification algorithms that might further improve GL performance.Comment: In Proceedings ACL2 2013, arXiv:1304.712