Doctor of Philosophy

dissertationA modern software system is a composition of parts that are themselves highly complex: operating systems, middleware, libraries, servers, and so on. In principle, compositionality of interfaces means that we can understand any given module independently of the internal workings of other parts. In practice, however, abstractions are leaky, and with every generation, modern software systems grow in complexity. Traditional ways of understanding failures, explaining anomalous executions, and analyzing performance are reaching their limits in the face of emergent behavior, unrepeatability, cross-component execution, software aging, and adversarial changes to the system at run time. Deterministic systems analysis has a potential to change the way we analyze and debug software systems. Recorded once, the execution of the system becomes an independent artifact, which can be analyzed offline. The availability of the complete system state, the guaranteed behavior of re-execution, and the absence of limitations on the run-time complexity of analysis collectively enable the deep, iterative, and automatic exploration of the dynamic properties of the system. This work creates a foundation for making deterministic replay a ubiquitous system analysis tool. It defines design and engineering principles for building fast and practical replay machines capable of capturing complete execution of the entire operating system with an overhead of several percents, on a realistic workload, and with minimal installation costs. To enable an intuitive interface of constructing replay analysis tools, this work implements a powerful virtual machine introspection layer that enables an analysis algorithm to be programmed against the state of the recorded system through familiar terms of source-level variable and type names. To support performance analysis, the replay engine provides a faithful performance model of the original execution during replay

Using embedded hardware monitor cores in critical computer systems

The integration of FPGA devices in many different architectures and services makes monitoring and real time detection of errors an important concern in FPGA system design. A monitor is a tool, or a set of tools, that facilitate analytic measurements in observing a given system. The goal of these observations is usually the performance analysis and optimisation, or the surveillance of the system. However, System-on-Chip (SoC) based designs leave few points to attach external tools such as logic analysers. Thus, an embedded error detection core that allows observation of critical system nodes (such as processor cores and buses) should enforce the operation of the FPGA-based system, in order to prevent system failures. The core should not interfere with system performance and must ensure timely detection of errors. This thesis is an investigation onto how a robust hardware-monitoring module can be efficiently integrated in a target PCI board (with FPGA-based application processing features) which is part of a critical computing system. [Continues.

Dyretiva: um método para a verificação das restrições temporais em sistemas embarcados

The Dyretiva is a method used for verifying the time constraints of embedded realtime systems. The verification is performed by monitoring the embedded software when it is running in an embedded hardware. The Dyretiva method takes into account the resource constrained nature of embedded systems and the time bounded nature of real-time systems. The method is comprised by a monitoring approach and a fault model. The monitoring approach defines the physical and the logical interfaces used in the observation of the system under test, as well as the strategies used for an optimized trace data collection. The fault model identifies relationships and components of the system under test that are most likely to have time faults. To demonstrate Dyretiva concepts, a set of support tools called SoftScope has been developed. SoftScope is comprised of a source code pre-instrumentation tool, a source code instrumentation tool, a hybrid monitor, a program for controlling the hybrid monitor, programs for filtering and analyzing trace data, and a graphical presentation tool. The Dyretiva method and the SoftScope tool set are an integral part of the work-inprogress PERF project, which is under development in the LIT (Laboratory of Embedded Systems Innovation and Technology), at the UTFPR (Federal Technological University of Paraná State). The objective of the PERF project is to build a complete environment suitable for the development of embedded and real-time systems.O Dyretiva é um método desenvolvido para utilização na fase de testes de sistemas embarcados operando em tempo real e, em especial, na verificação das restrições temporais do sistema. Como a fase de testes situa-se no final do processo de desenvolvimento, quando o hardware está disponível e o software codificado, a verificação temporal é feita por meio de monitoração do sistema sob teste. As principais premissas do Dyretiva são considerar a limitação de recursos dos sistemas embarcados e as características intrínsecas dos sistemas em tempo real. O método é definido por uma abordagem de monitoração e por um modelo de falta. A abordagem de monitoração define a interface física e lógica necessárias para observar o sistema sob teste, bem como as estratégias de utilização que permitem otimizar a coleta de dados. O modelo de falta identifica as relações e componentes do sistema onde existe maior probabilidade de encontrar os erros procurados. Para demonstrar os conceitos do Dyretiva, um conjunto de ferramentas de apoio a aplicação do método foi construído. Este conjunto, chamado de SoftScope, é composto por seis ferramentas: um pré-instrumentador de código, um instrumentador de código, um monitor, um programa de controle do monitor, programas para filtragem e análise dos dados capturados e um programa de visualização dos resultados. O Dyretiva e o SoftScope são parte integrante do projeto PERF, que está em andamento no LIT (Laboratório de Inovação e Tecnologia em Sistemas Embarcados) da UTFPR (Universidade Tecnológica Federal do Paraná), cujo objetivo é construir um ambiente completo para o desenvolvimento de sistemas embarcados operando em tempo real