Modulo scheduling with integrated register spilling for clustered VLIW architectures

Clustering is a technique to decentralize the design of future wide issue VLIW cores and enable them to meet the technology constraints in terms of cycle time, area and power dissipation. In a clustered design, registers and functional units are grouped in clusters so that new instructions are needed to move data between them. New aggressive instruction scheduling techniques are required to minimize the negative effect of resource clustering and delays in moving data around. In this paper we present a novel software pipelining technique that performs instruction scheduling with reduced register requirements, register allocation, register spilling and inter-cluster communication in a single step. The algorithm uses limited backtracking to reconsider previously taken decisions. This backtracking provides the algorithm with additional possibilities for obtaining high throughput schedules with low spill code requirements for clustered architectures. We show that the proposed approach outperforms previously proposed techniques and that it is very scalable independently of the number of clusters, the number of communication buses and communication latency. The paper also includes an exploration of some parameters in the design of future clustered VLIW cores.Peer ReviewedPostprint (published version

Behavioral synthesis from VHDL using structured modeling

This dissertation describes work in behavioral synthesis involving the development of a VHDL Synthesis System VSS which accepts a VHDL behavioral input specification and performs technology independent synthesis to generate a circuit netlist of generic components. The VHDL language is used for input and output descriptions. An intermediate representation which incorporates signal typing and component attributes simplifies compilation and facilitates design optimization.A Structured Modeling methodology has been developed to suggest standard VHDL modeling practices for synthesis. Structured modeling provides recommendations for the use of available VHDL description styles so that optimal designs will be synthesized.A design composed of generic components is synthesized from the input description through a process of Graph Compilation, Graph Criticism, and Design Compilation. Experiments were performed to demonstrate the effects of different modeling styles on the quality of the design produced by VSS. Several alternative VHDL models were examined for each benchmark, illustrating the improvements in design quality achieved when Structured Modeling guidelines were followed

Hierarchical clustered register file organization for VLIW processors

Technology projections indicate that wire delays will become one of the biggest constraints in future microprocessor designs. To avoid long wire delays and therefore long cycle times, processor cores must be partitioned into components so that most of the communication is done locally. In this paper, we propose a novel register file organization for VLIW cores that combines clustering with a hierarchical register file organization. Functional units are organized in clusters, each one with a local first level register file. The local register files are connected to a global second level register file, which provides access to memory. All intercluster communications are done through the second level register file. This paper also proposes MIRS-HC, a novel modulo scheduling technique that simultaneously performs instruction scheduling, cluster selection, inserts communication operations, performs register allocation and spill insertion for the proposed organization. The results show that although more cycles are required to execute applications, the execution time is reduced due to a shorter cycle time. In addition, the combination of clustering and hierarchy provides a larger design exploration space that trades-off performance and technology requirements.Peer ReviewedPostprint (published version

Silicon compilation

Silicon compilation is a term used for many different purposes. In this paper we define silicon compilation as a mapping from some higher level description into layout. We define the basic issues in structural and behavioral silicon compilation and some possible solutions to those issues. Finally, we define the concept of an intelligent silicon compiler in which the compiler evaluates the quality of the generated design and attempts to improve it if it is not satisfactory

Encoding techniques for complex information structures in connectionist systems

Two general information encoding techniques called relative position encoding and pattern similarity association are presented. They are claimed to be a convenient basis for the connectionist implementation of complex, short term information processing of the sort needed in common sense reasoning, semantic/pragmatic interpretation of natural language utterances, and other types of high level cognitive processing. The relationships of the techniques to other connectionist information-structuring methods, and also to methods used in computers, are discussed in detail. The rich inter-relationships of these other connectionist and computer methods are also clarified. The particular, simple forms are discussed that the relative position encoding and pattern similarity association techniques take in the author's own connectionist system, called Conposit, in order to clarify some issues and to provide evidence that the techniques are indeed useful in practice

Chippe : a system for constraint driven behavioral synthesis

This report describes the Chippe system, gives some background previous work and describes several sample design runs of the system. Also presented are the sources of the design tradeoffs used by Chippe, and overview of the internal design model, and experiences using the system

Multinet : enabler for next generation enterprise wireless services

Wireless communications are currently experiencing a fast migration toward the beyond third-generation (B3G)/fourth generation (4G) era. This represents a generational change in wireless systems: new capabilities related to mobility and new services support is required and new concepts as individual-centric, user-centric or ambient-aware communications are included. One of the main restrictions associated to wireless technology is mobility management, this feature was not considered in the design phase; for this reason, a complete solution is not already found, although different solutions are proposed and are being proposed. In MULTINET project, features as mobility and multihoming are applied to wireless network to provide the necessary network and application functionality enhancements for seamless data communication mobility considering end-user scenario and preferences. The aim of this paper is to show the benefits of these functionalities from the Service Providers and final User point of view

The de Soto Effect

This paper explores the consequences of creating and improving property rights so thatfixed assets can be used as collateral. This has become a cause célèbre of Hernando de Sotowhose views are influential in debates about policy reform concerning property rights.Hence, we refer to the economic impact of such reforms as the de Soto effect. We explore thelogic of the argument for credit contracts, both in isolation, and in market equilibrium. Weshow that the impact will vary with the degree of market competition. Where competition isweak, it is possible that borrowers will be worse off when property rights improve. Wediscuss the implications for optimal policy and the political economy of policy reform.

Comparative analysis of the existing and proposed ETS

Emissions trading schemes (ETS) have been operational to control greenhouse gas emissions in European Union since 2005. Under the EU ETS, the governments of the Member States agree on national emission caps, allocate allowances to industrial operators, track and validate the actual emissions and retire allowances at the end of each year. ETS have been proposed to be introduced in New Zealand, Australia, Japan, US, Canada, Korea, India and two Chinese provinces in the near future. The main idea of the ETS is to create the market for pollution which will provide economic agents with incentives to reduce their emissions ( Stavins, et al., 2003). The design of ETS plays an important role in reducing greenhouse gas emissions and promoting environmental and economic sustainability. There are several designs of ETS including cap-and-trade, baseline-and-credit and hybrid, however, cap-and-trade scheme is the most popular among the proposed ETS. The purpose of this paper is to perform a comprehensive review of the existing and the proposed ETS focusing on design issues. Findings of this research will be useful for countries with existing and proposed ETS and for countries intending to adopt ETS in the future.Emission Trading Scheme (ETS), Sustainability, Cap-and-trade, Baseline-and-credit, Hybrid