Statistical Static Timing Analysis for Performance of Logic Gates

In the recent nanotechnology, the variation in the gate propagation delay is the big concern. This paper proposes the new model for gate delay propagation using the Statistical Static Timing Analysis and the results of it are compared with another modelling called as Monte-Carlo analysis. The proposed model uses Statistical analysis to find accurate propagation delay of the logic gates with reduced simulation time for 16nm technology. DOI: 10.17762/ijritcc2321-8169.15057

Statistical Static Timing Analysis for Digital Circuitry

This paper proposed the impact of variations on delay in CMOS technology of 32 nm. The magnitude of process variations have grown, there has been an increasing realization that traditional design methodologies both for analysis and optimization are no longer acceptable. The main objective of the project is that Statistical Static Timing Analysis method has the result closer to best method and less time consuming which is far more acceptable. So we consider Statistical Static timing Analysis is the best and acceptable method for timing analysis of digital Circuits. The variation in propagation delay is big concern. The proposed system considers the variations in the designing process and finds the propagation delay. This is compared with another method called as Monte Carlo method. Also the simulation time required for both the methods are considered