A 16-bit CORDIC rotator for high-performance wireless LAN

In this paper we propose a novel 16-bit low power CORDIC rotator that is used for high-speed wireless LAN. The algorithm converges to the final target angle by adaptively selecting appropriate iteration steps while keeping the scale factor virtually constant. The VLSI architecture of the proposed design eliminates the entire arithmetic hardware in the angle approximation datapath and reduces the number of iterations by 50% on an average. The cell area of the processor is 0.7 mm2 and it dissipates 7 mW power at 20 MHz frequency

Direct kinematics solution architectures for industrial robot manipulators: Bit-serial versus parallel

A Very Large Scale Integration (VLSI) architecture for robot direct kinematic computation suitable for industrial robot manipulators was investigated. The Denavit-Hartenberg transformations are reviewed to exploit a proper processing element, namely an augmented CORDIC. Specifically, two distinct implementations are elaborated on, such as the bit-serial and parallel. Performance of each scheme is analyzed with respect to the time to compute one location of the end-effector of a 6-links manipulator, and the number of transistors required

IMPLEMENTACIÓN EN CHIP VLSI DEL ALGORITMO CORDIC PARA LA SOLUCIÓN DE FUNCIONES TRIGONOMÉTRICAS (VLSI ON-CHIP IMPLEMENTATION OF THE CORDIC ALGORITHM FOR THE SOLUTION OF TRIGONOMETRIC FUNCTIONS)

En este trabajo se presenta una implementación del algoritmo CORDIC en tecnología VLSI con una arquitectura de 16 bits. Se propone una forma simplificada para resolver las funciones trigonométricas básicas por hardware con tiempos de ejecución de entre 16 y 36 ciclos de reloj. El diseño de la arquitectura fue sintetizada para fabricarse en un proceso de tecnología CMOS de 0.5 micras de On Semiconductor sobre una área de 1.88 mm². Este diseño nos habilita la generación de módulos IP aritméticos de alta eficiencia que nos permitirá el desarrollo de algoritmos en chips tipo ASIC indispensables en la línea de investigación de integración de sistemas digitales.Palabra(s) Clave: Diseño VLSI, Funciones trigonométricas, Alliance CAD System, Algoritmo en Hardware. AbstractIn this paper we present an implementation of the CORDIC algorithm in VLSI technology with a 16 bit architecture. A simplified form is proposed to solve the basic trigonometric functions by hardware with execution times of between 16 and 36 clock cycles. The design of the architecture was synthesized to be manufactured in a 0.5 micron CMOS technology process of On Semiconductor over an area of 1.88 mm². This design enables us to generate high efficiency arithmetic IP modules that will allow us to develop algorithms on ASIC-type chips that are indispensable in the digital systems integration research line.Keywords: VLSI Design, Square Root, Alliance CAD System, Algorithm on Chip

Design techniques for low-power wide-band direct digital frequency synthesizers of spread spectrum communication applications

For frequency agile communication systems, fast frequency switching in fine frequency steps with good spectral purity is crucial. Direct Digital Frequency Synthesizer (DDFS) is best suitable for these applications, but is not widely employed in wireless communication systems due to its high power consumption. In general, low power and high integration design are two challenges for mixed signal-circuits and communication systems designers. In this dissertation, new design techniques for DDFS at both architecture and circuit levels are proposed and investigated in order to minimize power consumption and optimize performance. A ROM-less low power wide band DDFS prototype using segmented sine wave Digital-to-Analog Converter (DAC) were designed, fabricated and tested to demonstrate the new design techniques.;First, to further reduce power consumption and save chip area, two new phase interpolation ROM less DDFS architectures are proposed. Segmentation technique is applied to the design of sine wave DAC for DDFS: (1) based upon trigonometric identities, a segmented sine wave DAC with fine nonlinear interpolation DAC\u27s is proposed; (2) based upon first order Taylor series and simple linear interpolation, a segmented sine wave DAC with a fine linear interpolation DAC is proposed. Second, a figure of merit (FM) is defined to find the optimal sine wave DAC segmentations for various resolutions of the segmented sine wave DAC\u27s. The device mismatch effects on the performance of segmented sine wave were also discussed. Third, For DDFS using current-steering segmented sine wave DAC with 12-b phase resolution and 11-b amplitude resolution, a behavioral model in Verilog was used to verify the functionality and validate the architecture. Finally, a DDFS prototype was designed and fabricated in a standard 0.25mum CMOS process. The measured SFDR is better than 50 dB with output frequencies up to 3/8 of the 300 MHz clock frequency. The prototype occupies an active area of 1.4 mm2 and consumes 240 mW for 300 MHz clock frequency. The new techniques reduce the power dissipation and die area substantially when compared to conventional ROM based DDFS designs with on-chip DAC