A Scalable Correlator Architecture Based on Modular FPGA Hardware, Reuseable Gateware, and Data Packetization

A new generation of radio telescopes is achieving unprecedented levels of sensitivity and resolution, as well as increased agility and field-of-view, by employing high-performance digital signal processing hardware to phase and correlate large numbers of antennas. The computational demands of these imaging systems scale in proportion to BMN^2, where B is the signal bandwidth, M is the number of independent beams, and N is the number of antennas. The specifications of many new arrays lead to demands in excess of tens of PetaOps per second. To meet this challenge, we have developed a general purpose correlator architecture using standard 10-Gbit Ethernet switches to pass data between flexible hardware modules containing Field Programmable Gate Array (FPGA) chips. These chips are programmed using open-source signal processing libraries we have developed to be flexible, scalable, and chip-independent. This work reduces the time and cost of implementing a wide range of signal processing systems, with correlators foremost among them,and facilitates upgrading to new generations of processing technology. We present several correlator deployments, including a 16-antenna, 200-MHz bandwidth, 4-bit, full Stokes parameter application deployed on the Precision Array for Probing the Epoch of Reionization.Comment: Accepted to Publications of the Astronomy Society of the Pacific. 31 pages. v2: corrected typo, v3: corrected Fig. 1

Mapping our Universe in 3D with MITEoR

Mapping our universe in 3D by imaging the redshifted 21 cm line from neutral hydrogen has the potential to overtake the cosmic microwave background as our most powerful cosmological probe, because it can map a much larger volume of our Universe, shedding new light on the epoch of reionization, inflation, dark matter, dark energy, and neutrino masses. We report on MITEoR, a pathfinder low-frequency radio interferometer whose goal is to test technologies that greatly reduce the cost of such 3D mapping for a given sensitivity. MITEoR accomplishes this by using massive baseline redundancy both to enable automated precision calibration and to cut the correlator cost scaling from N^2 to NlogN, where N is the number of antennas. The success of MITEoR with its 64 dual-polarization elements bodes well for the more ambitious HERA project, which would incorporate many identical or similar technologies using an order of magnitude more antennas, each with dramatically larger collecting area.Comment: To be published in proceedings of 2013 IEEE International Symposium on Phased Array Systems & Technolog

Circuit design and analysis for on-FPGA communication systems

On-chip communication system has emerged as a prominently important subject in Very-Large- Scale-Integration (VLSI) design, as the trend of technology scaling favours logics more than interconnects. Interconnects often dictates the system performance, and, therefore, research for new methodologies and system architectures that deliver high-performance communication services across the chip is mandatory. The interconnect challenge is exacerbated in Field-Programmable Gate Array (FPGA), as a type of ASIC where the hardware can be programmed post-fabrication. Communication across an FPGA will be deteriorating as a result of interconnect scaling. The programmable fabrics, switches and the specific routing architecture also introduce additional latency and bandwidth degradation further hindering intra-chip communication performance. Past research efforts mainly focused on optimizing logic elements and functional units in FPGAs. Communication with programmable interconnect received little attention and is inadequately understood. This thesis is among the first to research on-chip communication systems that are built on top of programmable fabrics and proposes methodologies to maximize the interconnect throughput performance. There are three major contributions in this thesis: (i) an analysis of on-chip interconnect fringing, which degrades the bandwidth of communication channels due to routing congestions in reconfigurable architectures; (ii) a new analogue wave signalling scheme that significantly improves the interconnect throughput by exploiting the fundamental electrical characteristics of the reconfigurable interconnect structures. This new scheme can potentially mitigate the interconnect scaling challenges. (iii) a novel Dynamic Programming (DP)-network to provide adaptive routing in network-on-chip (NoC) systems. The DP-network architecture performs runtime optimization for route planning and dynamic routing which, effectively utilizes the in-silicon bandwidth. This thesis explores a new horizon in reconfigurable system design, in which new methodologies and concepts are proposed to enhance the on-FPGA communication throughput performance that is of vital importance in new technology processes

Cryogenic Control Beyond 100 Qubits

Quantum computation has been a major focus of research in the past two decades, with recent experiments demonstrating basic algorithms on small numbers of qubits. A large-scale universal quantum computer would have a profound impact on science and technology, providing a solution to several problems intractable for classical computers. To realise such a machine, today's small experiments must be scaled up, and a system must be built which provides control and measurement of many hundreds of qubits. A device of this scale is challenging: qubits are highly sensitive to their environment, and sophisticated isolation techniques are required to preserve the qubits' fragile states. Solid-state qubits require deep-cryogenic cooling to suppress thermal excitations. Yet current state-of-the-art experiments use room-temperature electronics which are electrically connected to the qubits. This thesis investigates various scalable technologies and techniques which can be used to control quantum systems. With the requirements for semiconductor spin-qubits in mind, several custom electronic systems, to provide quantum control from deep cryogenic temperatures, are designed and measured. A system architecture is proposed for quantum control, providing a scalable approach to executing quantum algorithms on a large number of qubits. Control of a gallium arsenide qubit is demonstrated using a cryogenically operated FPGA driving custom gallium arsenide switches. The cryogenic performance of a commercial FPGA is measured, as the main logic processor in a cryogenic quantum control system, and digital-to-analog converters are analysed during cryogenic operation. Recent work towards a 100-qubit cryogenic control system is shown, including the design of interconnect solutions and multiplexing circuitry. With qubit fidelity over the fault-tolerant threshold for certain error correcting codes, accompanying control platforms will play a key role in the development of a scalable quantum machine