높은 전류구동능력을 위한 Si/SiGe 물질을 가지는 터널링 전계효과 트랜지스터

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2015. 2. 박병국.For integrated circuits with highly-scaled complementary MOS (CMOS) technology, power dissipation problem has become an important issue since power per chip continues to increases and leakage power dominates in advanced technology nodes. In order to solve power issues, the supply voltage (VDD) scaling is very essential and devices which have low leakage current are needed. Recently, many research groups have studied a tunnel field-effect transistors (tunnel FETs) which is suitable for low operating power device. Tunnel FETs have very low leakage current and small subthrehold swing (SS) at room temperature unlike CMOS because of carrier injection using tunneling. In this thesis, a novel tunnel FET with SiGe body and elevated Si drain region have been proposed. The proposed tunnel FET has larger current drivability than conventional Si tunnel FETs because it uses a narrow bandgap material for low tunneling resistance. Also, it is expected that electrical characteristics can be improved by using SiGe channel and source for n-channel as well as p-channel operation. In addition, ambipolar current that is caused by band-to-band tunneling (BTBT) between channel and drain can be suppressed by using elevated Si drain region. For obtaining fundamental electrical properties of tunnel FET with SiGe body, planar structures are firstly fabricated and analyzed with Si tunnel FET. From electrical characteristics of fabricated devices, it is observed that both n-type and p-type SiGe tunnel FETs have better switching properties than Si devices. Current saturations become faster and drive current shows 10 times more than that of Si tunnel FETs. In addition, BTBT model parameters of Si and Ge materials in fabricated devices are extracted through TCAD simulation. Extracted A and B parameters of BTBT model in Si are 4×1014 cm-1s-1 and 9.9×106 V/cm. Also, A and B parameters of Ge can be extracted as 3.1×1016 cm-1s-1 and 7.1×105 V/cm, respectively. Using calibrated model parameters, proposed tunnel FET is simulated and optimized in terms of switching properties with changing Ge contents, effect of the elevated Si drain region, short-channel effects, inverter operation, and device delay. Based on these optimized simulation results, the proposed tunnel FET is fabricated using spacer technique because it is possible to make self-aligned doping process. Key unit process is as follows: epitaxial growth for Si and SiGe materials, e-beam lithography for active-fin formation, and sidewall spacer gate formation. For n-channel and p-channel operation, fabricated tunnel FET shows the better electrical characteristics than control groups. Extracted point SS is 51.1 mV/dec for p-type tunnel FET and 87 mV/dec for n-type tunnel FET. Ambipolar current of the proposed tunnel FET is suppressed to 1/100 of that of planar SiGe tunnel FET. Also, in order to analyze current flow mechanism of tunnel FET, the electrical characteristics are measured with temperature variation. As temperature goes up, Shockley-Read-Hall and field-dependent generation are increased resulting in degradation of switching property. In current saturation region, BTBT which has low temperature sensitivity is dominant on current property. From this study, it is demonstrated that the novel tunnel FET with SiGe body and the elevated Si drain shows improved electrical performance compared with Si tunnel FET. Also, both n-type and p-type devices can obtain high current drivability and small SS without structure changes. This means that the proposed device has strong advantage in terms of implementing IC with tunnel FET. Thus, it will be one of the promising candidates for next-generation devices.Abstract i Contents iv List of Figures vi Chapter 1 1 Introduction 1 1.1 POWER ISSUES ON CMOS TECHNOLOGIES 1 1.2 TUNNEL FIELD-EFFECT TRANSISTOR (TUNNEL FET) 3 1.3 ISSUES IN TUNNEL FET 6 1.4 SCOPE OF THESIS 9 Chapter 2 11 Planar Si and SiGe tunnel FETs 11 2.1 EXPITAXY GROWTH FOR SI AND SIGE LAYERS 11 2.2 SIGE MOSCAP AND MOSFET FABRICATION 14 2.3 PLANAR SI AND SIGE TUNNEL FET 15 2.4 SUMMARY 34 Chapter 3 35 Device Simulation 35 3.1 PROPOSED TUNNEL FET 35 3.2 SIMULATION PARAMETERS AND RESULTS 37 3.3 TRANSIENT RESPONSE CHARACTERISTICS 43 Chapter 4 51 Device Characteristics 51 4.1 PROCESS FLOW 51 4.2 ACTIVE FIN PATTERNING USING E-BEAM LITHOGRAPHY 54 4.3 DRAIN AND GATE FORMATION 56 4.4 DEVICE CHARACTERISTICS 61 4.5 REASON OF DEGRADED CHARACTERISTICS IN N-TYPE DEVICE 70 Chapter 5 73 Conclusions 73 Bibliography 77 초록 78Docto

Scaling and variability in ultra thin body silicon on insulator (UTB SOI) MOSFETs

The main objective of this thesis is to perform a comprehensive simulation study of the statistical variability in well scaled fully depleted ultra thin body silicon on insulator (FD-UTB SOI) at nanometer regime. It describes the design procedure for template FDUTB SOI transistor scaling and the impacts of statistical variability and reliability the scaled template transistor. The starting point of this study is a systematic simulation analysis based on a welldesigned 32nm thin body SOI template transistor provided by the FP7 project PULLNANO. The 32nm template transistor is consistent with the International Technology Roadmap for Semiconductor (ITRS) 2009 specifications. The wellestablished 3D ‘atomistic’ simulator GARAND has been employed in the designing of the scaled transistors and to carry out the statistical variability simulations. Following the foundation work in characterizing and optimizing the template 32 nm gate length transistor, the scaling proceeds down to 22 nm, 16 nm and 11 nm gate lengths using typically 0.7 scaling factor in respect of the horizontal and vertical transistor dimensions. The device design process is targeted for low power applications with a careful consideration of the impacts of the design parameters choice including buried oxide thickness (TBOX), source/drain doping abruptness (σ) and spacer length (Lspa). In order to determine the values of TBOX, σ, and Lspa, it is important to analyze simulation results, carefully assessing the impact on manufacturability and to consider the corresponding trade-off between short channel effects and on-current performance. Considering the above factors, TBOX = 10nm, σ = 2nm/dec and Lspa = 7nm have been adopted as optimum values respectively. iv The statistical variability of the transistor characteristics due to intrinsic parameter fluctuation (IPF) in well-scaled FD-UTB SOI devices is systematically studied for the first time. The impact of random dopant fluctuation (RDF), line edge roughness (LER) and metal gate granularity (MGG) on threshold voltage (Vth), on-current (Ion) and drain induced barrier lowering (DIBL) are analysed. Each principal sources of variability is treated individually and in combination with other variability sources in the simulation of large ensembles of microscopically different devices. The introduction of highk/ metal gate stack has improved the electrostatic integrity and enhanced the overall device performance. However, in the case of fully depleted channel transistors, MGG has become a dominant variability factor for all critical electrical parameters at gate first technology. For instance, σVth due to MGG increased to 41.9 mV at 11nm gate length compared to 26.0 mV at 22nm gate length. Similar trend has also been observed in σIon, increasing from 0.065 up to 0.174 mA/μm when the gate length is reduced from 22 nm down to 11 nm. Both RDF and LER have significant role in the intrinsic parameter fluctuations and therefore, none of these sources should be overlooked in the simulations. Finally, the impact of different variability sources in combination with positive bias temperature instability (PBTI) degradation on Vth, Ion and DIBL of the scaled nMOSFETs is investigated. Our study indicates that BTI induced charge trapping is a crucial reliability problem for the FD-UTB SOI transistors operation. Its impact not only introduces a significant degradation of transistor performance, but also accelerates the statistical variability. For example, the effect of a late degradation stage (at trap density of 1e12/cm2) in the presence of RDF, LER and MGG results in σVth increase to 36.9 mV, 45.0 mV and 58.3 mV for 22 nm, 16 nm and 11 nm respectively from the original 29.0 mV, 37.9 mV and 50.4 mV values in the fresh transistors

Low Power Design Techniques for Digital Logic Circuits.

With the rapid increase in the density and the size of chips and systems, area and power dissipationbecome critical concern in Very Large Scale Integrated (VLSI) circuit design. Low powerdesign techniques are essential for today's VLSI industry. The history of symbolic logic and sometypical techniques for finite state machine (FSM) logic synthesis are reviewed.The state assignment is used to optimize area and power dissipation for FSMs. Two costfunctions, targeting area and power, are presented. The Genetic Algorithm (GA) is used to searchfor a good state assignment to minimize the cost functions. The algorithm has been implementedin C. The program can produce better results than NOVA, which is integrated into SIS by DCBerkeley, and other publications both in area and power tested by MCNC benchmarks.Flip-flops are the core components of FSMs. The reduction of power dissipation from flip-flopscan save power for digital systems significantly. Three new kinds of flip-flops, called differentialCMOS single edge-triggered flip-flop with clock gating, double edge-triggered and multiple valuedflip-flops employing multiple valued clocks, are proposed. All circuits are simulated using PSpice.Most researchers have focused on developing low-power techniques in AND/OR or NAND& NOR based circuits. The low power techniques for AND /XOR based circuits are still intheir early stage of development. To implement a complex function involving many inputs,a form of decomposition into smaller subfunctions is required such that the subfunctions fitinto the primitive elements to be used in the implementation. Best polarity based XOR gatedecomposition technique has been developed, which targets low power using Huffman algorithm.Compared to the published results, the proposed method shows considerable improvement inpower dissipation. Further, Boolean functions can be expressed by Fixed Polarity Reed-Muller(FPRM) forms. Based on polarity transformation, an algorithm is developed and implementedin C language which can find the best polarity for power and area optimization. Benchmarkexamples of up to 21 inputs run on a personal computer are given

Diseño, Implementación y Verificación de un Sensor de Temperatura CMOS de Bajo Coste y Alta Funcionalidad

En este proyecto, se presenta un sensor de temperatura integrado CMOS basado en la medida de una variable secundaria, cuyo valor es dependiente de la temperatura, como es el tiempo de subida que presenta una señal eléctrica en sus flancos de subida. Con el objetivo de reducir coste y potencia consumida, el sensor integrado de temperatura propuesto genera un pulso con un ancho proporcional a la temperatura medida. Este sensor para realizar la medida elimina la necesidad de tener una señal que sirva de referencia. El área ocupada por este modelo de sensor es de 1.8967mm2, siendo éste fabricado en tecnología CMOS de 0.35µm de 4 capas de metal. Gracias a la excelente linealidad que presenta la salida digital del sensor, el error de medida alcanzado es como máximo de ±0.520ºC. La resolución efectiva mostrada en el caso peor es de 0.7ºC, y el consumo de potencia se encuentra por debajo de los 263µW, con una velocidad de realización de medidas que puede llegar a alcanzar las 1.5x10^6 medidas por segundo

Proceedings of the Caltech Conference on Very Large Scale Integration, held at the California Institute of Technology 22 - 24 January 1979 ; Organized by the Caltech Computer Science Department and the Caltech Industrial Associates Office

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