Redesigning a tagless access buffer to require minimal ISA changes

Energy efficiency is a first-order design goal for nearly all classes of processors, but it is particularly important in mobile and embedded systems. Data caches in such systems account for a large portion of the processor\u27s energy usage, and thus techniques to improve the energy efficiency of the cache hierarchy are likely to have high impact. Our prior work reduced data cache energy via a tagless access buffer (TAB) that sits at the top of the cache hierarchy. Strided memory references are redirected from the level-one data cache (L1D) to the smaller, more energy-efficient TAB. These references need not access the data translation lookaside buffer (DTLB), and they can avoid unnecessary transfers from lower levels of the memory hierarchy. The original TAB implementation requires changing the immediate field of load and store instructions, necessitating substantial ISA modifications. Here we present a new TAB design that requires minimal instruction set changes, gives software more explicit control over TAB resource management, and remains compatible with legacy (non-TAB) code. With a line size of 32 bytes, a four-line TAB can eliminate 31% of L1D accesses, on average. Together, the new TAB, L1D, and DTLB use 22% less energy than a TAB-less hierarchy, and the TAB system decreases execution time by 1.7%

Flexible Hardware-based Security-aware Mechanisms and Architectures

For decades, software security has been the primary focus in securing our computing platforms. Hardware was always assumed trusted, and inherently served as the foundation, and thus the root of trust, of our systems. This has been further leveraged in developing hardware-based dedicated security extensions and architectures to protect software from attacks exploiting software vulnerabilities such as memory corruption. However, the recent outbreak of microarchitectural attacks has shaken these long-established trust assumptions in hardware entirely, thereby threatening the security of all of our computing platforms and bringing hardware and microarchitectural security under scrutiny. These attacks have undeniably revealed the grave consequences of hardware/microarchitecture security flaws to the entire platform security, and how they can even subvert the security guarantees promised by dedicated security architectures. Furthermore, they shed light on the sophisticated challenges particular to hardware/microarchitectural security; it is more critical (and more challenging) to extensively analyze the hardware for security flaws prior to production, since hardware, unlike software, cannot be patched/updated once fabricated. Hardware cannot reliably serve as the root of trust anymore, unless we develop and adopt new design paradigms where security is proactively addressed and scrutinized across the full stack of our computing platforms, at all hardware design and implementation layers. Furthermore, novel flexible security-aware design mechanisms are required to be incorporated in processor microarchitecture and hardware-assisted security architectures, that can practically address the inherent conflict between performance and security by allowing that the trade-off is configured to adapt to the desired requirements. In this thesis, we investigate the prospects and implications at the intersection of hardware and security that emerge across the full stack of our computing platforms and System-on-Chips (SoCs). On one front, we investigate how we can leverage hardware and its advantages, in contrast to software, to build more efficient and effective security extensions that serve security architectures, e.g., by providing execution attestation and enforcement, to protect the software from attacks exploiting software vulnerabilities. We further propose that they are microarchitecturally configured at runtime to provide different types of security services, thus adapting flexibly to different deployment requirements. On another front, we investigate how we can protect these hardware-assisted security architectures and extensions themselves from microarchitectural and software attacks that exploit design flaws that originate in the hardware, e.g., insecure resource sharing in SoCs. More particularly, we focus in this thesis on cache-based side-channel attacks, where we propose sophisticated cache designs, that fundamentally mitigate these attacks, while still preserving performance by enabling that the performance security trade-off is configured by design. We also investigate how these can be incorporated into flexible and customizable security architectures, thus complementing them to further support a wide spectrum of emerging applications with different performance/security requirements. Lastly, we inspect our computing platforms further beneath the design layer, by scrutinizing how the actual implementation of these mechanisms is yet another potential attack surface. We explore how the security of hardware designs and implementations is currently analyzed prior to fabrication, while shedding light on how state-of-the-art hardware security analysis techniques are fundamentally limited, and the potential for improved and scalable approaches

Low-power instruction-caches design for embedded microprocessors

Ph.DDOCTOR OF PHILOSOPH

Determining protein interaction specificity of native and designed bZIP family transcription factors

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Biology, 2012.Page 428 blank. Cataloged from PDF version of thesis.Includes bibliographical references.Protein-protein interactions are important for almost all cellular functions. Knowing which proteins interact with one another is important for understanding protein function as well as for being able to disrupt their interactions. The basic leucine-zipper transcription factors (bZIPs) are a class of eukaryotic transcription factors that form either homodimers or heterodimers that bind to DNA in a site-specific manner. bZIPs are similar in sequence and structure, yet bZIP protein-protein interactions are specific, and this specificity is important for determining which DNA sites are bound. bZIP proteins have a simple structure that makes them experimentally tractable and well suited for developing models of interaction specificity. While current models perform well at being able to distinguish interactions from non-interactions, they are not fully accurate or able to predict interaction affinity. Our current understanding of protein interaction specificity is limited by the small number of large, high-quality interaction data sets that can be analyzed. For my thesis work I took a biophysical approach to experimentally measure the interactions of many native and designed bZIP and bZIP-like proteins in a high-throughput manner. The first method I used involved protein arrays containing small spots of bZIP-derived peptides immobilized on glass slides, which were probed with fluorescently labeled candidate protein partners. To improve upon this technique, I developed a solution-based FRET assay. In this experiment, two different dye-labeled versions of each protein are purified and mixed together at multiple concentrations to generate binding curves that quantify the affinity of each pair-wise interaction. Using the array assay, I identified novel interactions between human proteins and virally encoded bZIPs, characterized peptides designed to bind specifically to native bZIPs, and measured the interactions of a large set of synthetic bZIP-like coiled coils. Using the solution-based FRET assay, I quantified the bZIP interaction networks of five metazoan species and observed conservation as well as rewiring of interactions throughout evolution. Together, these studies have identified new interactions, created peptide reagents, identified sequence determinants of interaction specificity, and generated large amounts of interaction data that will help in the further understanding of bZIP protein interaction specificity.by Aaron W. Reinke.Ph.D