Reconfigurable SWP Operator for Multimedia Processing

International audienceFor performance enhancement, reconfigurable processors have to overcome the overheads of reconfigurations such as the complexity of the interconnection network and reconfiguration time. In processors dealing with multimedia applications these overheads can be reduced by providing the reconfigurability inside the processing units rather than at interconnection level. Due to the low precision data nature of multimedia applications, reconfiguration at operator level also provides additional speedup through parallel execution of low precision data. In this paper a pipelined architecture of a reconfigurable coarse grain subword parallel (SWP) operator is presented for multimedia applications. This operator not only eliminates the need of reconfiguration time but also provides the reconfigurability at both data size level (different pixel data sizes) and at operation level (different multimedia oriented operations). This ensures a better utilization of the processor resources and reduces the reconfiguration overheads significantly

High speed reconfigurable SWP operator for multimedia processing using redundant data representation

International audienceFor better performance and efficiency, high speed reconfigurable computation units are required in processor design. However the reconfiguration overheads like interconnection cost and reconfiguration time delay reduce the benefits of reconfigurable processors. At the same time within the arithmetic operators, the speed of operations on binary data cannot be increased beyond certain limits because of the inherited carry propagation at any stage of the addition. In this paper to address both reconfiguration and computation time issues, a high speed reconfigurable operator is proposed for multimedia applications. This operator provides reconfigurability at both the operation level (different multimedia oriented operations) and at the data size level (different pixel data sizes) through the use of multimedia oriented subword parallelism (SWP). The speed of the different arithmetic operations is improved through the use of a carry propagation free addition on the redundant data representation. For multimedia applications, this operator ensures reconfigurability with high resource utilization along with high speed operations

High speed reconfigurable SWP operator for multimedia processing using redundant data representation

International audienceFor better performance and efficiency, high speed reconfigurable computation units are required in processor design. However the reconfiguration overheads like interconnection cost and reconfiguration time delay reduce the benefits of reconfigurable processors. At the same time within the arithmetic operators, the speed of operations on binary data cannot be increased beyond certain limits because of the inherited carry propagation at any stage of the addition. In this paper to address both reconfiguration and computation time issues, a high speed reconfigurable operator is proposed for multimedia applications. This operator provides reconfigurability at both the operation level (different multimedia oriented operations) and at the data size level (different pixel data sizes) through the use of multimedia oriented subword parallelism (SWP). The speed of the different arithmetic operations is improved through the use of a carry propagation free addition on the redundant data representation. For multimedia applications, this operator ensures reconfigurability with high resource utilization along with high speed operations