A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

A Discrete-Time Mixing Receiver Architecture with Wideband Image and Harmonic Rejection for Software-Defined Radio

A discrete-time mixing architecture for software defined radio receivers is proposed. It exploits 8x RF voltage oversampling followed by charge domain weighting to achieve 40dB 3rd and 5th harmonic rejection without channel bandwidth limitations. Also noise folding is reduced by 3dB. A zero-IF downconverter chip in 65nm CMOS can receive RF signals up to 900MHz, with NFmin=12dB, IIP3=11dBm at <20mW power consumption including multi-phase clock\ud generation

Towards a Universal Multi-Standard RF Receiver

Future wireless communication market calls for the need of an extreme compact wireless device that can easily access to all the available services at any time and at any location with minimum power consumption and cost. The key is to find a multi-standard wireless receiver that can cover all the service specifications while keeping redundant components to minimum. Reconfigurable concept is right fit the need. In this thesis, a fully integrated universal multi-standard receiver using low-cost CMOS technology has been proposed based on the survey for different wireless receiver specifications and optimum architectures. Tunable receiver building blocks such as filters, LNAs, Mixers, VCOs, gain blocks are the main factor to approach this novel receiver. In order to realize frequency agility, low cost as well as low power consumption, a good switch is a must. In this thesis, MEMS switches are preferred rather than active switches or active tuning elements based on their performance comparisons. In the feasibility study, as an example, first, a reconfigurable LNA and a reconfigurable oscillator using hard wires as switches have been developed, and then a LNA and an oscillator have been designed using a MEMS switch. The effect of hard-wire connection and MEMS to the circuits has been evaluated. No performance degradation has been found when using hard-wire connections, while some has been observed when using MEMS. However, MEMS could be integrated with other circuits on the same die if it could be built on low resistive silicon substrate without performance degradation

An Energy-Efficient Reconfigurable Mobile Memory Interface for Computing Systems

The critical need for higher power efficiency and bandwidth transceiver design has significantly increased as mobile devices, such as smart phones, laptops, tablets, and ultra-portable personal digital assistants continue to be constructed using heterogeneous intellectual properties such as central processing units (CPUs), graphics processing units (GPUs), digital signal processors, dynamic random-access memories (DRAMs), sensors, and graphics/image processing units and to have enhanced graphic computing and video processing capabilities. However, the current mobile interface technologies which support CPU to memory communication (e.g. baseband-only signaling) have critical limitations, particularly super-linear energy consumption, limited bandwidth, and non-reconfigurable data access. As a consequence, there is a critical need to improve both energy efficiency and bandwidth for future mobile devices.;The primary goal of this study is to design an energy-efficient reconfigurable mobile memory interface for mobile computing systems in order to dramatically enhance the circuit and system bandwidth and power efficiency. The proposed energy efficient mobile memory interface which utilizes an advanced base-band (BB) signaling and a RF-band signaling is capable of simultaneous bi-directional communication and reconfigurable data access. It also increases power efficiency and bandwidth between mobile CPUs and memory subsystems on a single-ended shared transmission line. Moreover, due to multiple data communication on a single-ended shared transmission line, the number of transmission lines between mobile CPU and memories is considerably reduced, resulting in significant technological innovations, (e.g. more compact devices and low cost packaging to mobile communication interface) and establishing the principles and feasibility of technologies for future mobile system applications. The operation and performance of the proposed transceiver are analyzed and its circuit implementation is discussed in details. A chip prototype of the transceiver was implemented in a 65nm CMOS process technology. In the measurement, the transceiver exhibits higher aggregate data throughput and better energy efficiency compared to prior works

Analysis of Impact of Transformer Coupled Input Matching on Concurrent Dual-Band Low Noise Amplifier

Emerging advancements in telecommunication system need robust radio devices which can capable of working multiple frequency bands seamlessly. In any Radio Frequency (RF) receiver architecture, Low Noise Amplifier (LNA) is the mandatory front-end part in which takes place in between antenna and mixer. To support multiple frequency bands with single hardware, concurrent LNA is the more preferred topologies among others. As LNA is the very front end level of receiver, Input matching, Noise Figure (NF) and gain are the major performance parameters to be concerned. In this work, the impact of transformer coupled input matching on concurrent dual-band LNA is analyzed and verified. A concurrent LNA with concurrent matching without transformer coupling is used for comparison. A transformer coupled input matching is proposed for tunable concurrent dual-band LNA. All the circuits are implemented in UMC 180nm CMOS technology, and simulated using Cadence SpectreRF simulation tool

Digitally-Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference

A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR receiver: out-of-band nonlinearity and harmonic mixing. Voltage gain at RF is avoided, and instead realized at baseband in combination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative “iterative” harmonic-rejection (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multiphase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS. Measurements show 34 dB gain, 4 dB NF, and 3.5 dBm in-band IIP3 while the out-of-band IIP3 is + 16 dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order HR > dB over 40 chips, while the digital AIC technique achieves HR > 80 dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply

Full Duplex CMOS Transceiver with On-Chip Self-Interference Cancelation

abstract: The demand for the higher data rate in the wireless telecommunication is increasing rapidly. Providing higher data rate in cellular telecommunication systems is limited because of the limited physical resources such as telecommunication frequency channels. Besides, interference with the other users and self-interference signal in the receiver are the other challenges in increasing the bandwidth of the wireless telecommunication system. Full duplex wireless communication transmits and receives at the same time and the same frequency which was assumed impossible in the conventional wireless communication systems. Full duplex wireless communication, compared to the conventional wireless communication, doubles the channel efficiency and bandwidth. In addition, full duplex wireless communication system simplifies the reusing of the radio resources in small cells to eliminate the backhaul problem and simplifies the management of the spectrum. Finally, the full duplex telecommunication system reduces the costs of future wireless communication systems. The main challenge in the full duplex wireless is the self-interference signal at the receiver which is very large compared to the receiver noise floor and it degrades the receiver performance significantly. In this dissertation, different techniques for the antenna interface and self-interference cancellation are proposed for the wireless full duplex transceiver. These techniques are designed and implemented on CMOS technology. The measurement results show that the full duplex wireless is possible for the short range and cellular wireless communication systems.Dissertation/ThesisDoctoral Dissertation Engineering 201

Design of a Magnetically Tunable Low Noise Amplifier in 0.13 um CMOS Technology

With legacy technologies present and approaching new wireless standards, the 1-10 GHz band of frequencies is quickly becoming saturated. Although saturated, the frequency bands are being utilized inefficiently. Cognitive radio, an intelligent wireless communication system, is the novel solution for the efficient utilization of the frequency bands. Front-end receivers for cognitive radio will need the capability to receive and process multiple frequency bands and a key component is the low noise amplifier (LNA). A tunable LNA using a new magnetically tuned input impedance matching network is presented. The LNA has been designed and simulated in a commercially available 0.13 μm CMOS technology and is capable of tuning from 3.2 GHz to 4.6 GHz as S11 \u3c -10 dB. Within this bandwidth the maximum power gain is 16.2 dB, the maximum noise figure is 7.5 dB, and the minimum IIP3 is -6.4 dBm. The total power consumption of the LNA (neglecting the buffer required to drive the 50 Ω test equipment) is 50 mW. This tunable LNA introduces a new magnetically tunable matching technique and tuning scheme capable of continuous frequency variation for LNAs. It is expected that this technique could be expanded to realize LNAs with a tunable, narrow-band response that can cover the entire 1-10 GHz band of frequencies. The presented tunable LNA has demonstrated the capability to cover and process multiple frequencies and can be used for reconfigurable systems. A tunable LNA design is the first step in an effort to realize a fully reconfigurable front-end radio frequency (RF) receiver for future cognitive radio applications

Flexible CMOS low-noise amplifiers for beyond-3G wireless hand-held devices

This paper explores the use of reconfigurable Low-Noise Amplifiers (LNAs) for the implementation of CMOS Radio Frequency (RF) front-ends in the next generation of multi-standard wireless transceivers. Main circuit strategies reported so far for multi-standard LNAs are reviewed and a novel flexible LNA intended for Beyond-3G RF hand-held terminals is presented. The proposed LNA circuit consists of a two-stage topology that combines inductive-source degeneration with PMOS-varactor based tuning network and a programmable load to adapt its performance to different standard specifications without penalizing the circuit noise and with a reduced number of inductors as compared to previous reported reconfigurable LNAs. The circuit has been designed in a 90-nm CMOS technology to cope with the requirements of the GSM, WCDMA, Bluetooth and WLAN (IEEE 802.11b-g) standards. Simulation results, including technology and packaging parasitics, demonstrate correct operation of the circuit for all the standards under study, featuring NF13.3dB and IIP3>10.9dBm, over a 1.85GHz-2.4GHz band, with an adaptive power consumption between 17mW and 22mW from a 1-V supply voltage. Preliminary experimental measurements are included, showing a correct reconfiguration operation within the operation band