Rank-Modulation Rewrite Coding for Flash Memories

The current flash memory technology focuses on the cost minimization of its static storage capacity. However, the resulting approach supports a relatively small number of program-erase cycles. This technology is effective for consumer devices (e.g., smartphones and cameras) where the number of program-erase cycles is small. However, it is not economical for enterprise storage systems that require a large number of lifetime writes. The proposed approach in this paper for alleviating this problem consists of the efficient integration of two key ideas: 1) improving reliability and endurance by representing the information using relative values via the rank modulation scheme and 2) increasing the overall (lifetime) capacity of the flash device via rewriting codes, namely, performing multiple writes per cell before erasure. This paper presents a new coding scheme that combines rank-modulation with rewriting. The key benefits of the new scheme include: 1) the ability to store close to 2 bit per cell on each write with minimal impact on the lifetime of the memory and 2) efficient encoding and decoding algorithms that make use of capacity-achieving write-once-memory codes that were proposed recently

Compressed Encoding for Rank Modulation

Rank modulation has been recently proposed as a scheme for storing information in flash memories. While rank modulation has advantages in improving write speed and endurance, the current encoding approach is based on the "push to the top" operation that is not efficient in the general case. We propose a new encoding procedure where a cell level is raised to be higher than the minimal necessary subset -instead of all - of the other cell levels. This new procedure leads to a significantly more compressed (lower charge levels) encoding. We derive an upper bound for a family of codes that utilize the proposed encoding procedure, and consider code constructions that achieve that bound for several special cases

Rewriting Codes for Joint Information Storage in Flash Memories

Memories whose storage cells transit irreversibly between states have been common since the start of the data storage technology. In recent years, flash memories have become a very important family of such memories. A flash memory cell has q states—state 0.1.....q-1 - and can only transit from a lower state to a higher state before the expensive erasure operation takes place. We study rewriting codes that enable the data stored in a group of cells to be rewritten by only shifting the cells to higher states. Since the considered state transitions are irreversible, the number of rewrites is bounded. Our objective is to maximize the number of times the data can be rewritten. We focus on the joint storage of data in flash memories, and study two rewriting codes for two different scenarios. The first code, called floating code, is for the joint storage of multiple variables, where every rewrite changes one variable. The second code, called buffer code, is for remembering the most recent data in a data stream. Many of the codes presented here are either optimal or asymptotically optimal. We also present bounds to the performance of general codes. The results show that rewriting codes can integrate a flash memory’s rewriting capabilities for different variables to a high degree

Reliability and Hardware Implementation of Rank Modulation Flash Memory

We review a novel data representation scheme for NAND flash memory named rank modulation (RM), and discuss its hardware implementation. We show that under the normal threshold voltage (Vth) variations, RM has intrinsic read reliability advantage over conventional multiple-level cells. Test results demonstrating superior reliability using commercial flash chips are reviewed and discussed. We then present a read method based on relative sensing time, which can obtain the rank of all cells in the group in one read cycle. The improvement in reliability and read speed enable similar program-and-verify time in RM as that of conventional MLC flash

Storage Techniques in Flash Memories and Phase-change Memories

Non-volatile memories are an emerging storage technology with wide applica- tions in many important areas. This study focuses on new storage techniques for flash memories and phase-change memories. Flash memories are currently the most widely used type of non-volatile memory, and phase-change memories (PCMs) are the most promising candidate for the next-generation non-volatile memories. Like magnetic recording and optical recording, flash memories and PCMs have their own distinct properties, which introduce very interesting data storage problems. They include error correction, cell programming and other coding problems that affect the reliability and efficiency of data storage. Solutions to these problems can signifi- cantly improve the longevity and performance of the storage systems based on flash memories and PCMs. In this work, we study several new techniques for data storage in flash memories and PCMs. First, we study new types of error-correcting codes for flash memories – called error scrubbing codes –that correct errors by only increasing cell levels. Error scrubbing codes can correct errors without the costly block erasure operations, and we show how they can outperform conventional error-correcting codes. Next, we study the programming strategies for flash memory cells, and present an adaptive algorithm that optimizes the expected precision of cell programming. We then study data storage in PCMs, where thermal interference is a major challenge for data reliability. We present two new coding techniques that reduce thermal interference, and study their storage capacities and code constructions

Algorithms and Data Representations for Emerging Non-Volatile Memories

The evolution of data storage technologies has been extraordinary. Hard disk drives that fit in current personal computers have the capacity that requires tons of transistors to achieve in 1970s. Today, we are at the beginning of the era of non-volatile memory (NVM). NVMs provide excellent performance such as random access, high I/O speed, low power consumption, and so on. The storage density of NVMs keeps increasing following Moore’s law. However, higher storage density also brings significant data reliability issues. When chip geometries scale down, memory cells (e.g. transistors) are aligned much closer to each other, and noise in the devices will become no longer negligible. Consequently, data will be more prone to errors and devices will have much shorter longevity. This dissertation focuses on mitigating the reliability and the endurance issues for two major NVMs, namely, NAND flash memory and phase-change memory (PCM). Our main research tools include a set of coding techniques for the communication channels implied by flash memory and PCM. To approach the problems, at bit level we design error correcting codes tailored for the asymmetric errors in flash and PCM, we propose joint coding scheme for endurance and reliability, error scrubbing methods for controlling storage channel quality, and study codes that are inherently resisting to typical errors in flash and PCM; at higher levels, we are interested in analyzing the structures and the meanings of the stored data, and propose methods that pass such metadata to help further improve the coding performance at bit level. The highlights of this dissertation include the first set of write-once memory code constructions which correct a significant number of errors, a practical framework which corrects errors utilizing the redundancies in texts, the first report of the performance of polar codes for flash memories, and the emulation of rank modulation codes in NAND flash chips

Coding Techniques for Error Correction and Rewriting in Flash Memories

Flash memories have become the main type of non-volatile memories. They are widely used in mobile, embedded and mass-storage devices. Flash memories store data in floating-gate cells, where the amount of charge stored in cells – called cell levels – is used to represent data. To reduce the level of any cell, a whole cell block (about 106 cells) must be erased together and then reprogrammed. This operation, called block erasure, is very costly and brings significant challenges to cell programming and rewriting of data. To address these challenges, rank modulation and rewriting codes have been proposed for reliably storing and modifying data. However, for these new schemes, many problems still remain open. In this work, we study error-correcting rank-modulation codes and rewriting codes for flash memories. For the rank modulation scheme, we study a family of one- error-correcting codes, and present efficient encoding and decoding algorithms. For rewriting, we study a family of linear write-once memory (WOM) codes, and present an effective algorithm for rewriting using the codes. We analyze the performance of our solutions for both schemes