2 research outputs found
Impact of gate tunnelling leakage on CMOS circuits with full open defects
Electronics Letter of the MonthInterconnecting lines with full open defects become floating lines. In nanometric CMOS technologies, gate tunnelling leakage currents impact the behaviour of these lines, which cannot be considered
electrically isolated anymore. The voltage of the floating node is determined by its neighbours and leakage currents. After some time an equilibrium is reached between these effects. Theoretical analysis and experimental evidence of this behaviour are presented.Peer ReviewedAward-winningPostprint (published version