Compilation for heterogeneous SoCs : bridging the gap between software and target-specific mechanisms

International audienceCurrent applications constraints are pushing for higher computation power while reducing energy consumption, driving the development of increasingly specialized socs. In the mean time, these socs are still programmed in assembly language to make use of their specific hardware mechanisms. The constraints on hardware development bringing specialization, hence heterogeneity, it is essential to support these new mechanisms using high-level programming. In this work, we use a parametric data flow formalism to abstract the application from any hardware platform. From this premise, we propose to contribute to the compilation of target independent programs on heterogeneous platforms. These developments are threefold, with 1) the support of hardware accelerators for computation using actor fusion, 2) the automatic generation of communications on complex memory layouts and 3) the synchronization of distributed cores using hardware mechanisms for scheduling. The code generation is illustrated on a telecommunication dedicated heterogeneous soc

Achlys : Towards a framework for distributed storage and generic computing applications for wireless IoT edge networks with Lasp on GRiSP

Internet of Things (IoT) has gained substantial attention over the past years. And the main discussion has been how to process the amount of data that it generates which has lead to the edge computing paradigm. Wether it is called fog1, edge or mist, the principle remains that cloud services must become available closer to clients. This documents presents ongoing work on future edge systems that are built to provide steadfast IoT services to users by bringing storage and processing power closer to peripheral parts of networks. Designing such infrastructures is becoming much more challenging as the number of IoT devices keeps growing. Production grade deployments have to meet very high performance requirements, and end-to-end solutions involve significant investments. In this paper, we aim at providing a solution to extend the range of the edge model to the very farthest nodes in the network. Specifically, we focus on providing reliable storage and computation capabilities immediately on wireless IoT sensor nodes. This extended edge model will allow end users to manage their IoT ecosystem without forcibly relying on gateways or Internet provider solutions. In this document, we introduce Achlys, a prototype implementation of an edge node that is a concrete port of the Lasp programming library on the GRiSP Erlang embedded system. This way, we aim at addressing the need for a general purpose edge that is both resilient and consistent in terms of storage and network. Finally, we study example use cases that could take advantage of integrating the Achlys framework and discuss future work for the latter.Comment: 7 page

A Compilation Flow for Parametric Dataflow: Programming Model, Scheduling, and Application to Heterogeneous MPSoC

International audienceEfficient programming of signal processing applications on embedded systems is a complex problem. High level models such as Synchronous dataflow (SDF) have been privileged candidates for dealing with this complexity. These models permit to express inherent application parallelism, as well as analysis for both verification and optimization. Parametric dataflow models aim at providing sufficient dynamicity to model new applications, while at the same time maintaining the high level of analyzability needed for efficient real life implementations. This paper presents a new compilation flow that targets parametric dataflows. Built on the LLVM compiler infrastructure, it offers an actor based C++ programming model to describe parametric graphs, a compilation front-end providing graph analysis features, and a retargetable back-end to map the application on real hardware. This paper gives an overview of this flow, with a specific focus on scheduling. The crucial gap between dataflow models and real hardware on which actor firing is not atomic, as well as the consequences on FIFOs sizing and execution pipelining are taken into account.The experimental results illustrate our compilation flow applied to compilation of 3GPP LTE-Advanced demodulation on a heterogeneous MPSoC with distributed scheduling features. This achieves performances similar to time-consuming hand made optimizations

Implementing a Radio Virtual Machine on the MAGALI chip

International audienceTime to market is a key for commercial success of a SDR chip. Reusing hardware and reusing modern software development paradigms are the means to achieve a shorter time to market. Our work concerns the fast and portable development of new physical layer protocols (or waveforms) expressed in software, referred as "SDR programs". "Develop once, run anywhere" is the objective for SDR programs. It consists in providing full portability of waveforms between SDR platforms. To reach this portability the waveform specification must be expressed independently of its implementation, but also the executable specification should be, in some sense, independent of the implementation platform. Indeed, an SDR application should be able to download new waveform programs without knowing the implementation details of the chip it runs on. This problem can be solved with the use of a virtual machine: each SDR platform embed a virtual machine (VM) tuned to its own architectural details. All these VMs are able to interpret the same waveform executable specification expressed in a byte-code format. In this study we propose a virtual-machine based programming model applied to SDR that we call "Radio Virtual Machine" (RVM)

The Radio Virtual Machine: A Solution for SDR Portability and Platform Reconfigurability

International audienceIn this study we have presented a software architecture based on the virtual machine concept for SDR implementation. A high level abstraction language for the specification of PHY layer configurations has been proposed. In order to validate our concept and prove its practicality we have implemented IEEE802.11a PHY transmit and receive functionalities on a software demonstrator based on the Lua VM. This experiment has shown that both programming and execution mode

Highly efficient representation of reconfigurable code based on a radio virtual machine:optimization to any target platform

Abstract ETSI has developed a novel Software Radio Reconfiguration framework encompassing technical, certification and security solutions. Compared to legacy Software Reconfiguration technology, such as the Software Communications Architecture, the ETSI solution is designed for lowest overall power consumption and efficiency. For this purpose, a novel approach for Code Portability has been developed — a Radio Virtual Machine based mechanism allows converting a given algorithm into a generic representation, which is then, optimized for the specific hardware resources available on a target platform. This contribution explains the basic principles and outlines how Code Portability is achieved while meeting the objectives in terms of power consumption and complexity

Machine virtuelle pour la radio logicielle

Les architectures matérielles dédiées à la radio logicielle sont complexes à manipuler. L automatisation du passage de la modélisation à l implémentation a beaucoup d avantages et représente des enjeux économiques importants. Dans la littérature, les approches proposées de modélisation de la radio logicielle sont spécifiques à des plateformes particulières. Le passage à l implémentation se fait généralement par des techniques de compilation et de génération de code. Dans tous les cas, le programme exécutable généré est spécifique à une plateforme cible. Dans cette thèse, on propose un modèle de programmation orienté machine virtuelle qui permet d exprimer différents protocoles de niveau physique indépendamment de la plateforme cible. A ce modèle on associe un langage compilable vers un byte-code exécuté par la machine virtuelle radio (elle même est exécutée par un processeur natif ou réalisée par un matériel dédié) pour la configuration et le contrôle des plateformes radios. La machine virtuelle radio a été d abord expérimentée fonctionnellement sur une plateforme logicielle (PC) puis sur une plateforme réaliste avec considération des contraintes temps réel sur le système sur puce MAGALI (circuit du CEA-Leti). Pour valider le concept, des services de standards existants de couches physiques ont été implémentés. Les surcoûts de la machine virtuelle et du modèle de programmation ont été étudiés. Une évaluation quantitative expérimentale de ce surcoût a été réalisée et des techniques d optimisations ont été proposées.The hardware architectures dedicated to software radio are complex to handle. Automatic transition from modeling to implementation has many benefits and represents important economic perspectives. However the proposed approaches for software radios modeling, found in the state of the art, are specific to particular execution platforms. Indeed, moving to implementation is generally done through compilation and code generation techniques. In all cases, the generated executable program is definitively targeted for a specific platform. In this thesis, we propose a virtual machine based programming model which can express different physical layer protocols independently of the target platform. To this model we defined an associated language compilable into a high level byte-code to be executed by the radio virtual machine (which itself is executed by either a classic native processor or dedicated hardware) for configuration and control of radio platforms. The radio virtual machine was first tested functionally on a software platform (PC). Then, it has been experimented on a realistic platform with real-time constraints consideration: the CEA-Leti MAGALI chip. To validate the concept, several transmit and receive services of existing physical layer standards have been implemented. The additional costs of the virtual machine and the programming model were studied. Quantitative experimental evaluations of these additional costs have been realized and optimization techniques have been proposed.VILLEURBANNE-DOC'INSA LYON (692662301) / SudocSudocFranceF