4,345 research outputs found
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
In modern VLSI design flow, the register-transfer level (RTL) stage is a
critical point, where designers define precise design behavior with hardware
description languages (HDLs) like Verilog. Since the RTL design is in the
format of HDL code, the standard way to evaluate its quality requires
time-consuming subsequent synthesis steps with EDA tools. This time-consuming
process significantly impedes design optimization at the early RTL stage.
Despite the emergence of some recent ML-based solutions, they fail to maintain
high accuracy for any given RTL design. In this work, we propose an innovative
pre-synthesis PPA estimation framework named MasterRTL. It first converts the
HDL code to a new bit-level design representation named the simple operator
graph (SOG). By only adopting single-bit simple operators, this SOG proves to
be a general representation that unifies different design types and styles. The
SOG is also more similar to the target gate-level netlist, reducing the gap
between RTL representation and netlist. In addition to the new SOG
representation, MasterRTL proposes new ML methods for the RTL-stage modeling of
timing, power, and area separately. Compared with state-of-the-art solutions,
the experiment on a comprehensive dataset with 90 different designs shows
accuracy improvement by 0.33, 0.22, and 0.15 in correlation for total negative
slack (TNS), worst negative slack (WNS), and power, respectively.Comment: To be published in the Proceedings of 42nd IEEE/ACM International
Conference on Computer-Aided Design (ICCAD), 202
Rtl Power Estimation of Sequential Circuits
Power consumption has become a major concern in the electronic industry in recent years because of the increased demand for portable electronic devices. Part of the problem in power conscious design is accurate power estimation. Power estimation at low-levels of design abstraction is slow since the units of low-levels of design abstraction are transistors or gates. But designers need reliable power estimates early in the design process. Therefore designers need to have tools for fast and accurate power estimation at higher levels of design abstraction such as the Register Transfer Level (RTL).
This thesis introduces a new method for RTL power estimation of CMOS sequential circuits. This method tries to estimate the average power of a sequential circuit through the combination of a low-effort synthesis of the RTL description of the sequential circuit and the parameters readily available from the RTL description of the circuit like the sum-of-product count and literal count. The quantitative and qualitative aspects of the new model are studied with MCNC91 benchmark circuits and a large set of randomly generated circuits. Quantitative power estimation with the new model is seen to be very difficult because of the highly irregular surfaces of the functions that are being modeled in an effort to understand how a synthesis tool changes the power of a circuit during optimization. A qualitative measure is then proposed for the performance of a synthesis tool in preserving the qualitative ordering of power values of different implementations of a sequential circuit. An inference about such a performance of the synthesis tool would help the designer make informed decisions about the choice of implementation of a sequential circuit from a set of broad alternatives
From FPGA to ASIC: A RISC-V processor experience
This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC
Adaptive Modulation and Coding and Cooperative ARQ in a Cognitive Radio System
In this paper, a joint cross-layer design of adaptive modulation and coding
(AMC) and cooperative automatic repeat request (C-ARQ) scheme is proposed for a
secondary user in a shared-spectrum environment. First, based on the
statistical descriptions of the channel, closed-form expressions of the average
spectral efficiency (SE) and the average packet loss rate (PLR) are presented.
Then, the cross-layer scheme is designed, with the aim of maximizing the
average SE while maintaining the average PLR under a prescribed level. An
optimization problem is formed, and a sub-optimal solution is found: the target
packet error rates (PER) for the secondary system channels are obtained and the
corresponding sub-optimal AMC rate adaptation policy is derived based on the
target PERs. Finally, the average SE and the average PLR performance of the
proposed scheme are presented
- …