12,176 research outputs found

    Fast, area-efficient 32-bit LNS for computer arithmetic operations

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    PhD ThesisThe logarithmic number system has been proposed as an alternative to floating-point. Multiplication, division and square-root operations are accomplished with fixedpoint arithmetic, but addition and subtraction are considerably more challenging. Recent work has demonstrated that these operations too can be done with similar speed and accuracy to their floating-point equivalents, but the necessary circuitry is complex. In particular, it is dominated by the need for large lookup tables for the storage of a non-linear function. This thesis describes the architectures required to implement a newly design approach for producing fast and area-efficient 32-bit LNS arithmetic unit. The designs are structured based on two different algorithms. At first, a new cotransformation procedure is introduced in the singularity region whilst performing subtractions in which the technique capable to generate less total storage than the cotransformation method in the previous LNS architecture. Secondly, improvement to an existing interpolation process is proposed, that also reduce the total tables to an extent that allows their easy synthesis in logic. Consequently, the total delays in the system can be significantly reduced. According to the comparison analysis with previous best LNS design and floating-point units, it is shown that the new LNS architecture capable to offer significantly better in speed while sustaining its accuracy within floating-point limit. In addition, its implementation is more economical than previous best LNS system and almost equivalent with existing floating-point arithmetic unit.University Malaysia Perlis: Ministry of Higher Education, Malaysia

    QUALITY SORTING AND TRADE: FIRM-LEVEL EVIDENCE FOR FRENCH WINE

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    Quality sorting and trade: Firm-level evidence for French wine Investigations of the effect of quality differences on heterogeneous performance in exporting have been limited by lack of direct measures of quality. We examine exports of French wine, matching the exporting firms to producer ratings from two wine guides. We show that high quality producers export to more markets, charge higher prices, and sell more in each market. More attractive markets are served by exporters that, on average, make lower rated Champagne. Market attractiveness has a weakly negative effect on prices and a strongly positive effect on quantities, confirming the sign predictions of a simple quality sorting model. Methodologically, we make several contributions to the literature. First, we propose an estimation method for regressions of firm-level exports on ability measures and use Monte Carlo simulations to show that it corrects a severe selection bias present in OLS estimates. Second, we show how the means of quality, price, and quantity for exporters to a given market can be used to recover estimates of core parameters (which we compare with firm-level estimates) and discriminate between productivity and quality-sorting versions of the Melitz model. Our new method regresses country means on an index of each country's attractiveness and the fixed costs of entering it. We compare our method, which utilizes explanatory variables estimated in the firm-level regressions, to the conventional approach that relies on a reduced-form relationship with proxies for attractiveness and fixed costs.Industrial Organization, F12,

    The Cowl - v.10 - n.15 - Mar 17, 1948

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    The Cowl - student newspaper of Providence College. Volume 10, Number 15 - Mar 17, 1948. 4 pages

    The Design of a Processing Element for the Systolic Array Implementation of a Kalman Filter

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    The Kalman filter is an important component of optimal estimation theory. It has applications in a wide range of high performance control systems including navigational, fire control, and targeting systems. The Kalman filter, however, has not been utilized to its full potential due to the limitations of its inherent computational intensiveness which requires off-line processing or allows only low bandwidth real-time applications. The recent advances in VLSI circuit technology have created the opportunity to design algorithms and data structures for direct implementation in integrated circuits. A systolic architecture is a concept which allows the construction of massively parallel systems in integrated circuits and has been utilized as a means of achieving high data rates. A systolic system consists of a set of interconnected processing elements, each capable of performing some simple operation. The design of a processing element in an orthogonal systolic architecture will be investigated using the state of the art in VLSI technology. The goal is to create a high speed, high precision processing element which is adaptive to a highly configurable systolic architecture. In order to achieve the necessary high computational throughput, the arithmetic unit of the processing element will be implemented using the Logarithmic Number System. The Systolic architecture approach will be used in an attempt to implement a Kalman filtering system with both a high sampling rate and a small package size. The design of such a Kalman filter would enable this filtering technology to be applied to the areas of process control, computer vision, and robotics
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