Memory Fault Simulator for Static-Linked Faults

Static linked faults are considered an interesting class of memory faults. Their capability of influencing the behavior of other faults causes the hiding of the fault effect and makes test algorithm design and validation a very complex task. This paper presents a memory fault simulator architecture targeting the full set of linked fault

DFT and BIST of a multichip module for high-energy physics experiments

Engineers at Politecnico di Torino designed a multichip module for high-energy physics experiments conducted on the Large Hadron Collider. An array of these MCMs handles multichannel data acquisition and signal processing. Testing the MCM from board to die level required a combination of DFT strategie

Influence of parasitic capacitance variations on 65 nm and 32 nm predictive technology model SRAM core-cells

The continuous improving of CMOS technology allows the realization of digital circuits and in particular static random access memories that, compared with previous technologies, contain an impressive number of transistors. The use of new production processes introduces a set of parasitic effects that gain more and more importance with the scaling down of the technology. In particular, even small variations of parasitic capacitances in CMOS devices are expected to become an additional source of faulty behaviors in future technologies. This paper analyzes and compares the effect of parasitic capacitance variations in a SRAM memory circuit realized with 65 nm and 32 nm predictive technology model

March Test Generation Revealed

Memory testing commonly faces two issues: the characterization of detailed and realistic fault models and the definition of time-efficient test algorithms. Among the different types of algorithms proposed for testing static random access memories, march tests have proven to be faster, simpler, and regularly structured. The majority of the published march tests have been manually generated. Unfortunately, the continuous evolution of the memory technology introduces new classes of faults such as dynamic and linked faults and makes the task of handwriting test algorithms harder and not always leading to optimal results. Although some researchers published handmade march tests able to deal with new fault models, the problem of a comprehensive methodology to automatically generate march tests addressing both classic and new fault models is still an open issue. This paper proposes a new polynomial algorithm to automatically generate march tests. The formal model adopted to represent memory faults allows the definition of a general methodology to deal with static, dynamic, and linked faults. Experimental results show that the new automatically generated march tests reduce the test complexity and, therefore, the test time, compared to the well-known state of the art in memory testin

Optimizing Ram Testing Method For Test Time Saving Using Automatic Test Equipment

Due to the memory size increase drastically in the field programable gate array (FPGA) or system on chip (SOC) device, it become hard to meet the tests cost budget of the product especial for low-cost device. One of the major factor of test cost contributed is the test time. For the low-cost product, the tolerance number of the defects per million (DPM) are relative high compare to high cost product. By taking this advantage, an optimizing memory testing method able to implement to minimize the test time without jeopardize the test coverage. A memory Build-in Self-test (BIST) design with capability of algorithm failing sequence capture have been developed to implement in the Automate Test Equipment (ATE) flow for production screen. 3 selected algorithm have been tested on the 8 detect units in ATE flow to prove the concept of this method. The failing algorithm sequence of the units have been logged into database and analyzed for algorithm trimming. With the proper examples, the algorithm trimming location and test time saving calculation have been shown in this research. For this examples, approximate 33% of test time reduction observed for 1Kbyte memory testing with Hammer Head algorithm. In summary, this research has proposed the memory test time saving by optimizing the tests algorithm on the ATE flow

Flash-memories in Space Applications: Trends and Challenges

Nowadays space applications are provided with a processing power absolutely overcoming the one available just a few years ago. Typical mission-critical space system applications include also the issue of solid-state recorder(s). Flash-memories are nonvolatile, shock-resistant and power-economic, but in turn have different drawbacks. A solid-state recorder for space applications should satisfy many different constraints especially because of the issues related to radiations: proper countermeasures are needed, together with EDAC and testing techniques in order to improve the dependability of the whole system. Different and quite often contrasting dimensions need to be explored during the design of a flash-memory based solid- state recorder. In particular, we shall explore the most important flash-memory design dimensions and trade-offs to tackle during the design of flash-based hard disks for space application

March AB, a State-of-the-Art March Test for Realistic Static Linked Faults and Dynamic Faults in SRAMs

Memory testing commonly faces two issues: the characterisation of detailed and realistic fault models, and the definition of time-efficient test algorithms able to detect them. Among the different types of algorithms proposed for testing static random access memories (SRAMs), march tests have proven to be faster, simpler and regularly structured. The continuous evolution of the memory technology requires the constant introduction of new classes of faults, such as dynamic and linked faults. Presented here is March AB, a march test targeting realistic memory static linked faults and dynamic unlinked faults. Comparison results show that the proposed march test provides the same fault coverage of already published algorithms reducing the test complexity and therefore the test tim

Fsm-Based Enhanced March C- Algorithm For Memory Built-In Self-Test

Algorithms plays an important role in the Memory Built-In Self-Test as its structure will define the fault coverage of the system. Thus, the improvement of the algorithms will allow more fault types being identified in single test. For MARCH C- algorithm, it was a quite balance algorithm as it has the ability to cover Address Decoder Fault, Stuck-At Fault, Transition Fault and Coupling Fault but it was not able to identify Read Destructive Fault and Data Retention Fault. To increase the fault coverage of the MARCH C- algorithm on that two fault types, some enhancements were needed to make on the algorithm. Through the analysis of the fault patterns and other algorithm, it was found that multiple read operation within a single MARCH element from MARCH-NU algorithm can aid in the identification of the Read Destructive Fault whereas having HOLD time in the MARCH 9N algorithm would expose the Data Retention Fault. By integrating both new fault identification methodologies into the MARCH C- algorithm and enhance it so that it would able to increase the identification of the Data Retention Fault and Read Destructive Fault by 100% and without causing any performance to interfere with the original fault identification ability. Besides that, the enhanced MARCH C- algorithm can structurally identify the fault types and differentiate among the behavioural faults (Data Retention Faults) and common memory faults as well as among Stuck-At Fault and Transition Fault. Fault injection test were carried out to ensure the coverage of the enhanced MARCH C- algorithm. It was having high passing rate which are 100% v identification of the Stuck-At Fault, Transition Fault, Data Retention Fault, Inversion Read Fault, Incorrect Read Fault and Read Destructive Fault. It also obtained 95.16% for the State Coupling Fault and Idempotent Coupling Fault. As a conclusion, the enhanced MARCH C- algorithm had increased its fault type identification in Data Retention Fault and Read Destructive Fault while having the ability to structurally identify the fault types

Fault Detection with Optimum March Test Algorithm

This paper presents a research work aimed to detect previously-undetected faults, either Write Disturb Faults (WDFs) or Deceptive Read Destructive Faults (DRDFs) or both in March Algorithm such as MATS++(6N), March C-(10N), March SR(14N), and March CL(12N). The main focus of this research is to improve fault coverage on Single Cell Faults as well as Static Double Cell Faults detection, using specified test algorithm. Transition Coupling Faults (CFtrs), Write Destructive Coupling Faults (CFwds) and Deceptive Read Destructive Faults (CFdrds) are types of faults mainly used in this research. The experiment result published in [1] shows BIST (Built-In-Self-Test) implementation with the new algorithm. It provides the same test length but with bigger area overhead, we therefore proposed a new 14N March Test Algorithm with fault coverage of more than 95% using solid 0s and 1s Data Background (DB). This paper reveals the design methodology to generate DB covers all memories function by applying non-transition data, transition data, and single read and double read data. The automation hardware was designed to give the flexibility to the user to generate other new March Algorithm prior to the selected algorithm and analyzed the performance in terms of fault detection and power consumption