Publicly Detectable Watermarking for Intellectual Property Authentication in VLSI Design

Highlighted with the newly released intellectual property (IP) protection white paper by VSI Alliance, the protection of virtual components or IPs in very large scale integration (VLSI) design has received a great deal of attention recently. Digital signature/watermark is one of the most promising solutions among the known protection mechanisms. It provides desirable proof of authorship without rendering the IP useless. However, it makes the watermark detection, which is as important as watermarking, an NP-hard problem. In fact, the tradeoff between hard-to-attack and easy-to-detect and the lack of efficient detection schemes are the major obstacles for digital signatures to thrive. In this paper, the authors propose a new watermarking method which allows the watermark to be publicly detected without losing its strength and security. The basic idea is to create a cryptographically strong pseudo-random watermark, embed it into the original problem as a special (which the authors call mutual exclusive) constraint, and make it public. The authors combine data integrity technique and the unique characteristics in the design of VLSI IPs such that adversaries will not gain any advantage from the public watermarking for forgery. This new technique is compatible with the existing constraint-based watermarking/fingerprinting techniques. The resulting public–private watermark maintains the strength of a watermark and provides easy detectability with little design overhead. The authors build the mathematical framework for this approach based on the concept of mutual exclusive constraints. They use popular VLSI CAD problems, namely technology mapping, partitioning, graph coloring, FPGA design, and Boolean satisfiability, to demonstrate the public watermark’s easy detectability, high credibility, low design overhead, and robustness

A Sequential Circuit-Based IP Watermarking Algorithm for Multiple Scan Chains in Design-for-Test

In Very Large Scale Integrated Circuits (VLSI) design, the existing Design-for-Test(DFT) based watermarking techniques usually insert watermark through reordering scan cells, which causes large resource overhead, low security and coverage rate of watermark detection. A novel scheme was proposed to watermark multiple scan chains in DFT for solving the problems. The proposed scheme adopts DFT scan test model of VLSI design, and uses a Linear Feedback Shift Register (LFSR) for pseudo random test vector generation. All of the test vectors are shifted in scan input for the construction of multiple scan chains with minimum correlation. Specific registers in multiple scan chains will be changed by the watermark circuit for watermarking the design. The watermark can be effectively detected without interference with normal function of the circuit, even after the chip is packaged. The experimental results on several ISCAS benchmarks show that the proposed scheme has lower resource overhead, probability of coincidence and higher coverage rate of watermark detection by comparing with the existing methods

Watermark Decoding Technique using Machine Learning for Intellectual Property Protection

The Watermarking is an Intellectual Property (IP) Protection method. It can ensure Field-Programmable Gate Array (FPGA) IPs from encroachment. The IP security of equipment and programming structures is the most significant prerequisite for some FPGA licensed innovation merchants. Advanced watermarking has become a creative innovation for IP assurance as of late. This paper proposes the Publicly Verifiable Watermarking plan for licensed innovation insurance in FPGA structure. The Zero-Knowledge Verification Protocol and Data Matrix strategy are utilized in this watermarking location method. The time stepping is likewise utilized with the zero-information check convention and it can versatility oppose the delicate data spillage and implanting assaults, and is along these lines hearty to the cheating from the prover, verifier, or outsider. The encryption keys are additionally utilized with the information lattice technique and it can restrict the watermark, and make the watermark vigorous against assaults. In this proposed zero-information technique zero rate asset, timing and watermarking overhead can be accomplished. The proposed zero-information watermarking plan causes zero overhead. In this proposed information lattice technique signal-rich-workmanship code picture, can be portrayed. The proposed information network watermarking plan encodes the copyright confirmation data. The zero-information confirmation convention and information grid technique proposed in this paper is executed by MATLAB R2014a in which C programming language is utilized in it and ModelSim 10.5b in which VHDL coding is utilized in it, are running on a PC. The combination instrument Xilinx ISE 14.5 is likewise used to confirm and actualize the watermarking plan

A Chaotic IP Watermarking in Physical Layout Level Based on FPGA

A new chaotic map based IP (Intellectual Property) watermarking scheme at physical design level is presented. An encrypted watermark is embedded into the physical layout of a circuit by configuring LUT (Lookup Table) as specific functions when it is placed and routed onto the FPGA (Field-Programmable Gate Array). The main contribution is the use of multiple chaotic maps in the processes of watermark design and embedding, which efficiently improves the security of watermark. A hashed chaotic sequence is used to scramble the watermark. Secondly, two pseudo-random sequences are generated by using chaotic maps. One is used to determine unused LUT locations, and the other divides the watermark into groups. The watermark identifies original owner and is difficult to detect. This scheme was tested on a Xilinx Virtex XCV600-6bg432 FPGA. The experimental results show that our method has low impact on functionality, short path delay and high robustness in comparison with other methods

A survey on security analysis of machine learning-oriented hardware and software intellectual property

Intellectual Property (IP) includes ideas, innovations, methodologies, works of authorship (viz., literary and artistic works), emblems, brands, images, etc. This property is intangible since it is pertinent to the human intellect. Therefore, IP entities are indisputably vulnerable to infringements and modifications without the owner’s consent. IP protection regulations have been deployed and are still in practice, including patents, copyrights, contracts, trademarks, trade secrets, etc., to address these challenges. Unfortunately, these protections are insufficient to keep IP entities from being changed or stolen without permission. As for this, some IPs require hardware IP protection mechanisms, and others require software IP protection techniques. To secure these IPs, researchers have explored the domain of Intellectual Property Protection (IPP) using different approaches. In this paper, we discuss the existing IP rights and concurrent breakthroughs in the field of IPP research; provide discussions on hardware IP and software IP attacks and defense techniques; summarize different applications of IP protection; and lastly, identify the challenges and future research prospects in hardware and software IP security

A Survey on IP Watermarking Techniques

Intellectual property (IP) block reuse is essential for facilitating the design process of system-on-a-chip. Sharing IP designs poses significant high security risks. Recently, digital watermarking emerged as a candidate solution for copyright protection of IP blocks. In this paper, we survey and classify different techniques used for watermarking IP designs. To this end, we defined several evaluation criteria, which can also be used as a benchmark for new IP watermarking developments. Furthermore, we established a comprehensive set of requirements for future IP watermarking techniques

A Robust FSM Watermarking Scheme for IP Protection of Sequential Circuit Design

Finite state machines (FSMs) are the backbone of sequential circuit design. In this paper, a new FSM watermarking scheme is proposed by making the authorship information a non-redundant property of the FSM. To overcome the vulnerability to state removal attack and minimize the design overhead, the watermark bits are seamlessly interwoven into the outputs of the existing and free transitions of state transition graph (STG). Unlike other transition-based STG watermarking, pseudo input variables have been reduced and made functionally indiscernible by the notion of reserved free literal. The assignment of reserved literals is exploited to minimize the overhead of watermarking and make the watermarked FSM fallible upon removal of any pseudo input variable. A direct and convenient detection scheme is also proposed to allow the watermark on the FSM to be publicly detectable. Experimental results on the watermarked circuits from the ISCAS'89 and IWLS'93 benchmark sets show lower or acceptably low overheads with higher tamper resilience and stronger authorship proof in comparison with related watermarking schemes for sequential functions

An internet-based IP protection scheme for circuit designs using linear feedback shift register (LFSR)-based locking

Abstract—Due to emerging trend of design reuse in VLSI circuits, the intellectual property (IP) of design faces serious challenges like forgery, theft, misappropriation etc. These in-creasing risks of design IP stored in design repositories, or the threat of hacking the same during its Internet-based trans-mission, mandates design file encryption and its appropriate watermarking. In this paper, we propose a novel Internet-based scheme to tackle this problem. Input to the proposed scheme is a generic graph corresponding to a digital system design. Watermarking of the graph and its encryption are achieved using a new linear feedback shift register(LFSR)-based locking scheme. The proposed scheme makes unauthorized disclosure of valuable designs almost infeasible, and can easily detect any alteration of the design file during transmission. It ensures authentication of the original designer as well as non-repudiation between the seller and the buyer. Empirical evidences on several well-known benchmark problem sets are encouraging. Index Terms—Intellectual property protection (IPP), Water-marking, Encryption, Decryption

ОБЗОР МЕТОДОВ РЕАЛИЗАЦИИ АППАРАТНЫХ ВОДЯНЫХ ЗНАКОВ В ЦИФРОВЫХ УСТРОЙСТВАХ ПРОГРАММИРУЕМОЙ ЛОГИКИ

Application of watermarking technology for the protection of digital devices and their descriptionsis considered. Primary definitions, models, categories of attacks, characteristics and classificationof watermarks are described. Hardware watermarking examples are shown.Рассматривается применение технологии водяных знаков для защиты цифровых устройств и их проектных описаний. Приводятся основные определения, модели, категории атак, характеристики, классификация водяных знаков для данной области. Описываются примеры использования аппаратных водяных знаков