Provably Good Global Buffering Using an Available Buffer Block Plan

To implement high-performance global interconnect without impacting the performance of existing blocks, the use of buffer blocks is increasingly popular in structured-custom and block-based ASIC/SOC methodologies. Recent works by Cong et al. [6] and Tang and Wong [25] give algorithms to solve the buffer block planning problem. In this paper we address the problem of how to perform buffering of global nets given an existing buffer block plan. Assuming as in [6, 25] that global nets have been already decomposed into two-pin connections, we give a provably good algorithm based on a recent approach of Garg and Konemann [8] and Fleischer [7]. Our method routes connections using available buffer blocks, such that required upper and lower bounds on buffer intervals -- as well as wirelength upper bounds per connection -- are satisfied. Unlike [6, 25], our model allows more than one buffer to be inserted into any given connection. In addition, our algorithm observes buffer parity constraints, i.e., it will choose to use an inverter or a buffer (= co-located pair of inverters) according to source and destination signal parity. The algorithm outperforms previous approaches [6] and has been validated on top-level layouts extracted from a recent high-end microprocessor design

Interconnect-driven floorplanning.

Sham Chiu Wing.Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.Includes bibliographical references (leaves 107-113).Abstracts in English and Chinese.Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Motivations --- p.1Chapter 1.2 --- Progress on the Problem --- p.2Chapter 1.3 --- Our Contributions --- p.3Chapter 1.4 --- Thesis Organization --- p.5Chapter 2 --- Preliminaries --- p.6Chapter 2.1 --- Introduction --- p.6Chapter 2.1.1 --- The Role of Floorplanning --- p.6Chapter 2.1.2 --- Wirelength Estimation --- p.7Chapter 2.1.3 --- Different Types of Floorplan --- p.8Chapter 2.2 --- Representations of Floorplan --- p.10Chapter 2.2.1 --- Polish Expressions --- p.10Chapter 2.2.2 --- Sequence Pair --- p.11Chapter 2.2.3 --- Bounded-Sliceline Grid (BSG) Structure --- p.13Chapter 2.2.4 --- O-Tree --- p.14Chapter 2.2.5 --- B*-Tree --- p.16Chapter 2.2.6 --- Corner Block List --- p.18Chapter 2.2.7 --- Twin Binary Tree --- p.19Chapter 2.2.8 --- Comparisons between Different Representations --- p.20Chapter 2.3 --- Algorithms of Floorplan Design --- p.20Chapter 2.3.1 --- Constraint Based Floorplanning --- p.21Chapter 2.3.2 --- Integer Programming Based Floorplanning --- p.21Chapter 2.3.3 --- Neural Learning Based Floorplanning --- p.22Chapter 2.3.4 --- Rectangular Dualization --- p.22Chapter 2.3.5 --- Simulated Annealing --- p.23Chapter 2.3.6 --- Genetic Algorithm --- p.23Chapter 2.4 --- Summary --- p.24Chapter 3 --- Literature Review on Interconnect-Driven Floorplanning --- p.25Chapter 3.1 --- Introduction --- p.25Chapter 3.2 --- Simulated Annealing Approach --- p.25Chapter 3.2.1 --- """Pepper - A Timing Driven Early Floorplanner""" --- p.25Chapter 3.2.2 --- """A Timing Driven Block Placer Based on Sequence Pair Model""" --- p.26Chapter 3.2.3 --- """Integrated Floorplanning and Interconnect Planning""" --- p.27Chapter 3.2.4 --- """Interconnect Driven Floorplanning with Fast Global Wiring Planning and Optimization""" --- p.27Chapter 3.3 --- Genetic Algorithm Approach --- p.28Chapter 3.3.1 --- "“Timing Influenced General-cell Genetic Floorplanning""" --- p.28Chapter 3.4 --- Force Directed Approach --- p.29Chapter 3.4.1 --- """Timing Influenced Force Directed Floorplanning""" --- p.29Chapter 3.5 --- Congestion Planning --- p.30Chapter 3.5.1 --- """On the Behavior of Congestion Minimization During Placement""" --- p.30Chapter 3.5.2 --- """Congestion Minimization During Placement""" --- p.31Chapter 3.5.3 --- "“Estimating Routing Congestion Using Probabilistic Anal- ysis""" --- p.31Chapter 3.6 --- Buffer Planning --- p.32Chapter 3.6.1 --- """Buffer Block Planning for Interconnect Driven Floor- planning""" --- p.32Chapter 3.6.2 --- """Routability Driven Repeater Block Planning for Interconnect- centric Floorplanning""" --- p.33Chapter 3.6.3 --- """Provably Good Global Buffering Using an Available Block Plan""" --- p.34Chapter 3.6.4 --- "“Planning Buffer Locations by Network Flows""" --- p.34Chapter 3.6.5 --- """A Practical Methodology for Early Buffer and Wire Re- source Allocation""" --- p.35Chapter 3.7 --- Summary --- p.36Chapter 4 --- Floorplanner with Fixed Buffer Planning [34] --- p.37Chapter 4.1 --- Introduction --- p.37Chapter 4.2 --- Overview of the Floorplanner --- p.38Chapter 4.3 --- Congestion Model --- p.38Chapter 4.3.1 --- Construction of Grid Structure --- p.39Chapter 4.3.2 --- Counting the Number of Routes at a Grid --- p.40Chapter 4.3.3 --- Buffer Location Computation --- p.41Chapter 4.3.4 --- Counting Routes with Blocked Grids --- p.42Chapter 4.3.5 --- Computing the Probability of Net Crossing --- p.43Chapter 4.4 --- Time Complexity --- p.44Chapter 4.5 --- Simulated Annealing --- p.45Chapter 4.6 --- Wirelength Estimation --- p.46Chapter 4.6.1 --- Center-to-center Estimation --- p.47Chapter 4.6.2 --- Corner-to-corner Estimation --- p.47Chapter 4.6.3 --- Intersection-to-intersection Estimation --- p.48Chapter 4.7 --- Multi-pin Nets Handling --- p.49Chapter 4.8 --- Experimental Results --- p.50Chapter 4.9 --- Summary --- p.51Chapter 5 --- Floorplanner with Flexible Buffer Planning [35] --- p.53Chapter 5.1 --- Introduction --- p.53Chapter 5.2 --- Overview of the Floorplanner --- p.54Chapter 5.3 --- Congestion Model --- p.55Chapter 5.3.1 --- Probabilistic Model with Variable Interval Buffer Inser- tion Constraint --- p.57Chapter 5.3.2 --- Time Complexity --- p.61Chapter 5.4 --- Buffer Planning --- p.62Chapter 5.4.1 --- Estimation of Buffer Usage --- p.62Chapter 5.4.2 --- Estimation of Buffer Resources --- p.69Chapter 5.5 --- Two-phases Simulated Annealing --- p.70Chapter 5.6 --- Wirelength Estimation --- p.72Chapter 5.7 --- Multi-pin Nets Handling --- p.73Chapter 5.8 --- Experimental Results --- p.73Chapter 5.9 --- Remarks --- p.76Chapter 5.10 --- Summary --- p.76Chapter 6 --- Global Router --- p.77Chapter 6.1 --- Introduction --- p.77Chapter 6.2 --- Overview of the Global Router --- p.77Chapter 6.3 --- Buffer Insertion Constraint and Congestion Constraint --- p.78Chapter 6.4 --- Multi-pin Nets Handling --- p.79Chapter 6.5 --- Routing Methodology --- p.79Chapter 6.6 --- Implementation --- p.80Chapter 6.7 --- Summary --- p.86Chapter 7 --- Interconnect-Driven Floorplanning by Alternative Packings --- p.87Chapter 7.1 --- Introduction --- p.87Chapter 7.2 --- Overview of the Method --- p.87Chapter 7.3 --- Searching Alternative Packings --- p.89Chapter 7.3.1 --- Rectangular Supermodules in Sequence Pair --- p.89Chapter 7.3.2 --- Finding rearrangable module sets --- p.90Chapter 7.3.3 --- Alternative Sequence Pairs --- p.94Chapter 7.4 --- Implementation --- p.97Chapter 7.4.1 --- Re-calculation of Interconnect Cost --- p.98Chapter 7.4.2 --- Cost Function --- p.101Chapter 7.4.3 --- Time Complexity --- p.101Chapter 7.5 --- Experimental Results --- p.101Chapter 7.6 --- Summary --- p.103Chapter 8 --- Conclusion --- p.105Bibliography --- p.10

Efficient approaches in interconnect-driven floorplanning.

Lai Tsz Wai.Thesis (M.Phil.)--Chinese University of Hong Kong, 2003.Includes bibliographical references (leaves 123-129).Abstracts in English and Chinese.Chapter 1 --- Introduction --- p.1Chapter 1.1 --- VLSI Design Cycle --- p.2Chapter 1.2 --- Physical Design Cycle --- p.4Chapter 1.3 --- Floorplanning --- p.7Chapter 1.3.1 --- Types of Floorplan and Floorplan Representations --- p.11Chapter 1.3.2 --- Interconnect-driven Floorplanning --- p.13Chapter 1.4 --- Motivations and Contributions --- p.17Chapter 1.5 --- Organization of this Thesis --- p.18Chapter 2 --- Literature Review on Floorplan Representation --- p.20Chapter 2.1 --- Slicing Floorplan Representation --- p.20Chapter 2.1.1 --- Normalized Polish Expression --- p.20Chapter 2.2 --- Non-slicing Floorplan Representations --- p.21Chapter 2.2.1 --- Sequence Pair (SP) --- p.21Chapter 2.2.2 --- Bounded-sliceline Grid (BSG) --- p.23Chapter 2.2.3 --- O-tree --- p.25Chapter 2.2.4 --- B*-tree --- p.26Chapter 2.3 --- Mosaic Floorplan Representations --- p.28Chapter 2.3.1 --- Corner Block List (CBL) --- p.28Chapter 2.3.2 --- Twin Binary Trees (TBT) --- p.31Chapter 2.3.3 --- Twin Binary Sequences (TBS) --- p.32Chapter 2.4 --- Summary --- p.34Chapter 3 --- Literature Review on Interconnect Optimization in Floorplan- ning --- p.37Chapter 3.1 --- Wirelength Estimation --- p.37Chapter 3.2 --- Congestion Optimization --- p.38Chapter 3.2.1 --- Integrated Floorplanning and Interconnect Planning --- p.41Chapter 3.2.2 --- Multi-layer Global Wiring Planning (GWP) --- p.43Chapter 3.2.3 --- Estimating Routing Congestion using Probabilistic Anal- ysis --- p.44Chapter 3.2.4 --- Congestion Minimization During Placement --- p.46Chapter 3.2.5 --- Modelling and Minimization of Routing Congestion --- p.48Chapter 3.3 --- Buffer Planning --- p.49Chapter 3.3.1 --- Buffer Clustering with Feasible Region --- p.51Chapter 3.3.2 --- Routability-driven Repeater Clustering Algorithm with Iterative Deletion --- p.55Chapter 3.3.3 --- Planning Buffer Locations by Network Flow --- p.58Chapter 3.3.4 --- Buffer Planning using Integer Multicommodity Flow --- p.60Chapter 3.3.5 --- Buffer Planning Problem using Tile Graph --- p.60Chapter 3.3.6 --- Probabilistic Analysis for Buffer Block Planning --- p.62Chapter 3.3.7 --- Fast Buffer Planning and Congestion Optimization --- p.63Chapter 3.4 --- Summary --- p.66Chapter 4 --- Congestion Evaluation: Wire Density Model --- p.68Chapter 4.1 --- Introduction --- p.68Chapter 4.2 --- Overview of Our Floorplanner --- p.70Chapter 4.3 --- Wire Density Model --- p.71Chapter 4.3.1 --- Computation of Ni --- p.72Chapter 4.3.2 --- Computation of Pi --- p.74Chapter 4.3.3 --- Usage of Mirror TBT --- p.76Chapter 4.4 --- Implementation --- p.76Chapter 4.4.1 --- Efficient Calculation of Ni --- p.76Chapter 4.4.2 --- Solving the LCA Problem Efficiently --- p.81Chapter 4.4.3 --- Cost Function --- p.81Chapter 4.4.4 --- Complexity --- p.81Chapter 4.5 --- Experimental Results --- p.82Chapter 4.6 --- Conclusion --- p.83Chapter 5 --- Buffer Planning: Simple Buffer Planning Method --- p.85Chapter 5.1 --- Introduction --- p.85Chapter 5.2 --- Variable Interval Buffer Insertion Constraint --- p.87Chapter 5.3 --- Overview of Our Floorplanner --- p.88Chapter 5.4 --- Buffer Planning --- p.89Chapter 5.4.1 --- Feasible Grids --- p.89Chapter 5.4.2 --- Table Look-up Approach --- p.89Chapter 5.5 --- Implementation --- p.91Chapter 5.5.1 --- Building the Look-up Tables --- p.91Chapter 5.5.2 --- An Example of Look-up Table Construction --- p.94Chapter 5.5.3 --- A Faster Approach for Building the Look-up Tables --- p.101Chapter 5.5.4 --- An Example of the Faster Look-up Table Construction --- p.105Chapter 5.5.5 --- I/O Pin Locations --- p.106Chapter 5.5.6 --- Cost Function --- p.110Chapter 5.5.7 --- Complexity --- p.111Chapter 5.6 --- Experimental Results --- p.112Chapter 5.6.1 --- Selected Value for A --- p.112Chapter 5.6.2 --- Performance of Our Floorplanner --- p.113Chapter 5.7 --- Conclusion --- p.116Chapter 6 --- Conclusion --- p.118Chapter A --- An Efficient Algorithm for the Least Common Ancestor Prob- lem --- p.120Bibliography --- p.12