Application of Module to Coding Theory: A Systematic Literature Review

A systematic literature review is a research process that identifies, evaluates, and interprets all relevant study findings connected to specific research questions, topics, or phenomena of interest. In this work, a thorough review of the literature on the issue of the link between module structure and coding theory was done. A literature search yielded 470 articles from the Google Scholar, Dimensions, and Science Direct databases. After further article selection process, 14 articles were chosen to be studied in further depth. The items retrieved were from the previous ten years, from 2012 to 2022. The PRISMA analytical approach and bibliometric analysis were employed in this investigation. A more detailed description of the PRISMA technique and the significance of the bibliometric analysis is provided. The findings of this study are presented in the form of brief summaries of the 14 articles and research recommendations. At the end of the study, recommendations for future development of the code structure utilized in the articles that are further investigated are made

Design, optimization and Real Time implementation of a new Embedded Chien Search Block for Reed-Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes on FPGA Board

The development of error correcting codes has been a major concern for communications systems. Therefore, RS and BCH (Reed-Solomon and Bose, Ray-Chaudhuri and Hocquenghem) are effective methods to improve the quality of digital transmission. In this paper a new algorithm of Chien Search block for embedded systems is proposed. This algorithm is based on a factorization of error locator polynomial. i.e, we can minimize an important number of logic gates and hardware resources using the FPGA card. Consequently, it reduces the power consumption with a percentage which can reach 40 % compared to the basic RS and BCH decoder. The proposed system is designed, simulated using the hardware description language (HDL) and Quartus development software. Also, the performance of the designed embedded Chien search block for decoder RS\BCH (255, 239) has been successfully verified by implementation on FPGA board

On Fault Tolerance Methods for Networks-on-Chip

Technology scaling has proceeded into dimensions in which the reliability of manufactured devices is becoming endangered. The reliability decrease is a consequence of physical limitations, relative increase of variations, and decreasing noise margins, among others. A promising solution for bringing the reliability of circuits back to a desired level is the use of design methods which introduce tolerance against possible faults in an integrated circuit. This thesis studies and presents fault tolerance methods for network-onchip (NoC) which is a design paradigm targeted for very large systems-onchip. In a NoC resources, such as processors and memories, are connected to a communication network; comparable to the Internet. Fault tolerance in such a system can be achieved at many abstraction levels. The thesis studies the origin of faults in modern technologies and explains the classification to transient, intermittent and permanent faults. A survey of fault tolerance methods is presented to demonstrate the diversity of available methods. Networks-on-chip are approached by exploring their main design choices: the selection of a topology, routing protocol, and flow control method. Fault tolerance methods for NoCs are studied at different layers of the OSI reference model. The data link layer provides a reliable communication link over a physical channel. Error control coding is an efficient fault tolerance method especially against transient faults at this abstraction level. Error control coding methods suitable for on-chip communication are studied and their implementations presented. Error control coding loses its effectiveness in the presence of intermittent and permanent faults. Therefore, other solutions against them are presented. The introduction of spare wires and split transmissions are shown to provide good tolerance against intermittent and permanent errors and their combination to error control coding is illustrated. At the network layer positioned above the data link layer, fault tolerance can be achieved with the design of fault tolerant network topologies and routing algorithms. Both of these approaches are presented in the thesis together with realizations in the both categories. The thesis concludes that an optimal fault tolerance solution contains carefully co-designed elements from different abstraction levelsSiirretty Doriast

The Telecommunications and Data Acquisition Report

This publication provides reports on work performed for the Office of Space Tracking and Data Systems (OSTDS). It reports on the activities of the deep space network (DSN) and the Ground Communications Facility (GCF). Topics discussed on the operation of the DSN include: (1) spacecraft-ground communications; (2) station control and system technology; and (3) capabilities for new projects for systems implementation. The GCF compatibility with packets and data compression is discussed. In geodynamics, the publication reports on the application of radio interferometry at microwave frequencies for geodynamic measurements

The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design

NASA Tech Briefs, April 1992

Topics covered include: New Product Ideas; Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Computer Programs; Mechanics; Machinery; Fabrication Technology; Mathematics and Information Sciences