8,682 research outputs found
Stochastic rounding and reduced-precision fixed-point arithmetic for solving neural ordinary differential equations
Although double-precision floating-point arithmetic currently dominates
high-performance computing, there is increasing interest in smaller and simpler
arithmetic types. The main reasons are potential improvements in energy
efficiency and memory footprint and bandwidth. However, simply switching to
lower-precision types typically results in increased numerical errors. We
investigate approaches to improving the accuracy of reduced-precision
fixed-point arithmetic types, using examples in an important domain for
numerical computation in neuroscience: the solution of Ordinary Differential
Equations (ODEs). The Izhikevich neuron model is used to demonstrate that
rounding has an important role in producing accurate spike timings from
explicit ODE solution algorithms. In particular, fixed-point arithmetic with
stochastic rounding consistently results in smaller errors compared to single
precision floating-point and fixed-point arithmetic with round-to-nearest
across a range of neuron behaviours and ODE solvers. A computationally much
cheaper alternative is also investigated, inspired by the concept of dither
that is a widely understood mechanism for providing resolution below the least
significant bit (LSB) in digital signal processing. These results will have
implications for the solution of ODEs in other subject areas, and should also
be directly relevant to the huge range of practical problems that are
represented by Partial Differential Equations (PDEs).Comment: Submitted to Philosophical Transactions of the Royal Society
Privacy Leakages in Approximate Adders
Approximate computing has recently emerged as a promising method to meet the
low power requirements of digital designs. The erroneous outputs produced in
approximate computing can be partially a function of each chip's process
variation. We show that, in such schemes, the erroneous outputs produced on
each chip instance can reveal the identity of the chip that performed the
computation, possibly jeopardizing user privacy. In this work, we perform
simulation experiments on 32-bit Ripple Carry Adders, Carry Lookahead Adders,
and Han-Carlson Adders running at over-scaled operating points. Our results
show that identification is possible, we contrast the identifiability of each
type of adder, and we quantify how success of identification varies with the
extent of over-scaling and noise. Our results are the first to show that
approximate digital computations may compromise privacy. Designers of future
approximate computing systems should be aware of the possible privacy leakages
and decide whether mitigation is warranted in their application.Comment: 2017 IEEE International Symposium on Circuits and Systems (ISCAS
Design of multimedia processor based on metric computation
Media-processing applications, such as signal processing, 2D and 3D graphics
rendering, and image compression, are the dominant workloads in many embedded
systems today. The real-time constraints of those media applications have
taxing demands on today's processor performances with low cost, low power and
reduced design delay. To satisfy those challenges, a fast and efficient
strategy consists in upgrading a low cost general purpose processor core. This
approach is based on the personalization of a general RISC processor core
according the target multimedia application requirements. Thus, if the extra
cost is justified, the general purpose processor GPP core can be enforced with
instruction level coprocessors, coarse grain dedicated hardware, ad hoc
memories or new GPP cores. In this way the final design solution is tailored to
the application requirements. The proposed approach is based on three main
steps: the first one is the analysis of the targeted application using
efficient metrics. The second step is the selection of the appropriate
architecture template according to the first step results and recommendations.
The third step is the architecture generation. This approach is experimented
using various image and video algorithms showing its feasibility
Evaluating critical bits in arithmetic operations due to timing violations
Various error models are being used in simulation of voltage-scaled arithmetic units to examine application-level tolerance of timing violations. The selection of an error model needs further consideration, as differences in error models drastically affect the performance of the application. Specifically, floating point arithmetic units (FPUs) have architectural characteristics that characterize its behavior. We examine the architecture of FPUs and design a new error model, which we call Critical Bit. We run selected benchmark applications with Critical Bit and other widely used error injection models to demonstrate the differences
Skyrmion Gas Manipulation for Probabilistic Computing
The topologically protected magnetic spin configurations known as skyrmions
offer promising applications due to their stability, mobility and localization.
In this work, we emphasize how to leverage the thermally driven dynamics of an
ensemble of such particles to perform computing tasks. We propose a device
employing a skyrmion gas to reshuffle a random signal into an uncorrelated copy
of itself. This is demonstrated by modelling the ensemble dynamics in a
collective coordinate approach where skyrmion-skyrmion and skyrmion-boundary
interactions are accounted for phenomenologically. Our numerical results are
used to develop a proof-of-concept for an energy efficient
() device with a low area imprint ().
Whereas its immediate application to stochastic computing circuit designs will
be made apparent, we argue that its basic functionality, reminiscent of an
integrate-and-fire neuron, qualifies it as a novel bio-inspired building block.Comment: 41 pages, 20 figure
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