Synthesis from specifications : basic concepts

The need has evolved for a synthesis tool at the computer system level. SpecSyn is one such tool. Basically, it will view the world as a set of chips communicating via protocols. Thus, an abstract specification would get synthesized into a set of one or more interconnected chips. From that point, detail is added to each chip's specification until its structure is synthesized or it is determined that a prefabricated chip similar in functionality can be used.Features of such a tool include executable specifications from which to synthesize, constraint driven partitioning of the specifications into components (chips) and synthesis of interfaces between them, translation into VHDL and synthesis into VHDL structures of micro-architectural components, and the use of other tools (e.g. MILO, a micro-architecture and logic optimizer, and LES, a layout expert system) to evaluate the quality of the chip layout generated from VHDL description.A major component of SpecSyn is SpecCharts, a high level specification language amenable to system level synthesis, able to represent designs from system to register transfer levels. The language consists of a hierarchy of states, represented in combined graphical and textual form, at the same time catering to the expression of concurrent behavior and specification of constraints. With it we have specified several Intel chips as well as higher level systems, and have found it to be quite powerful and easy to use.SpecSyn will have a graphical interface, from which the user can at any time view or edit a SpecChart, translate to VHDL and simulate, view statistics provided by estimators (such as area, speed, and pins), store and retrieve SpecCharts, apply basic Spec Chart operations, as well as apply the partitioning algorithms or interface synthesizer. Providing access to a wide range of tools, having a single language represent the design throughout the synthesis process, and having user specified constraints allow the user to have varying amounts of control over the synthesis process

Semantics and synthesis of signals in behavioral VHDL

Signals are a fundamental part of VHDL behavioral descriptions. There are many kinds of VHDL signals, each possesing complex and hence often misunderstood semantics. The result is that synthesis tools often inadequately address synthesis of signals. In this report, we first make clear the semantics of the various signal kinds shared by multiple processes through the use of conceptual hardware, rather than just text. Second, with the semantics firmly understood, we discuss techniques and issues in synthesizing actual hardware for shared signals. This information can be used to take a step towards synthesizing correct hardware from VHDL descriptions while greatly reducing current restrictions imposed by synthesis tools on allowable VHDL behavior

Design of a LAPD interface using the T7130 multichannel LAPD controller and the T715A synchronous protocol data formatter

As the ISDN telecommunications standard gains acceptance, there is an ever increasing need for intelligent interfaces to implement the L2 protocol known as LAPD. The T7130 MLC, the T7115A SPYDER-T and the MC68020 microprocessor were used to design a LAPD Interface that conforms to the LAPD protocol as specified by CCITT. The LAPD Interface utilizes a Shared Memory Array which is attached to the Data Link Processors in a single bus configuration. The SMA Arbitration Control allows access to the SMA on a prioritized basis and was implemented as a state machine using PAL\u27s. L2 drivers and L3 management software were written and used to test the operability of the interface via an emulator. The LAPD Interface was able to terminate 32 I-IDLC channels configured for LAPD operation with an average throughput of 942.42 messages per second. The LAPD Interface was also able to operate efficiently in an environment in which random errors of the order of 1E-6 were injected

Application of advanced on-board processing concepts to future satellite communications systems

An initial definition of on-board processing requirements for an advanced satellite communications system to service domestic markets in the 1990's is presented. An exemplar system architecture with both RF on-board switching and demodulation/remodulation baseband processing was used to identify important issues related to system implementation, cost, and technology development

Advanced engineering - Communications systems research

Communications systems research on information systems and on digital telemetry and command in Deep Space Networ

Building real-time embedded applications on QduinoMC: a web-connected 3D printer case study

Single Board Computers (SBCs) are now emerging with multiple cores, ADCs, GPIOs, PWM channels, integrated graphics, and several serial bus interfaces. The low power consumption, small form factor and I/O interface capabilities of SBCs with sensors and actuators makes them ideal in embedded and real-time applications. However, most SBCs run non-realtime operating systems based on Linux and Windows, and do not provide a user-friendly API for application development. This paper presents QduinoMC, a multicore extension to the popular Arduino programming environment, which runs on the Quest real-time operating system. QduinoMC is an extension of our earlier single-core, real-time, multithreaded Qduino API. We show the utility of QduinoMC by applying it to a specific application: a web-connected 3D printer. This differs from existing 3D printers, which run relatively simple firmware and lack operating system support to spool multiple jobs, or interoperate with other devices (e.g., in a print farm). We show how QduinoMC empowers devices with the capabilities to run new services without impacting their timing guarantees. While it is possible to modify existing operating systems to provide suitable timing guarantees, the effort to do so is cumbersome and does not provide the ease of programming afforded by QduinoMC.http://www.cs.bu.edu/fac/richwest/papers/rtas_2017.pdfAccepted manuscrip

Safety component-based approach and its application to ERTMS/ETCS on-board train control system

International audienceSafety-critical software is becoming more and more complex and at the same time it operates in frequently changing environments on which it reacts by reconfiguring its architecture. Thus, an appropriate modelling approach is needed to reduce the complexity of designing and to enable the verification of dynamic reconfiguration behaviour before the deployment at runtime. The paradigm of software component-based engineering provides an essential support for this. However, composing software from many reconfigurable components can lead to a huge number of possible compositional configurations difficult to handle at design time. Moreover, analysing all possible sequences of reconfiguration, including failure situations, is far beyond feasibility without an appropriate abstraction and granularity levels. In this paper, we propose a hierarchical component-based design approach to reduce the complexity of designing and to analyse the dynamic reconfiguration behaviour. We illustrate our approach with a case study derived from ERTMS/ETCS level 2

A complete design path for the layout of flexible macros

XIV+172hlm.;24c

Adjacency Matrix Based Energy Efficient Scheduling using S-MAC Protocol in Wireless Sensor Networks

Communication is the main motive in any Networks whether it is Wireless Sensor Network, Ad-Hoc networks, Mobile Networks, Wired Networks, Local Area Network, Metropolitan Area Network, Wireless Area Network etc, hence it must be energy efficient. The main parameters for energy efficient communication are maximizing network lifetime, saving energy at the different nodes, sending the packets in minimum time delay, higher throughput etc. This paper focuses mainly on the energy efficient communication with the help of Adjacency Matrix in the Wireless Sensor Networks. The energy efficient scheduling can be done by putting the idle node in to sleep node so energy at the idle node can be saved. The proposed model in this paper first forms the adjacency matrix and broadcasts the information about the total number of existing nodes with depths to the other nodes in the same cluster from controller node. When every node receives the node information about the other nodes for same cluster they communicate based on the shortest depths and schedules the idle node in to sleep mode for a specific time threshold so energy at the idle nodes can be saved.Comment: 20 pages, 2 figures, 14 tables, 5 equations, International Journal of Computer Networks & Communications (IJCNC),March 2012, Volume 4, No. 2, March 201