A static data flow simulation study at Ames Research Center

Demands in computational power, particularly in the area of computational fluid dynamics (CFD), led NASA Ames Research Center to study advanced computer architectures. One architecture being studied is the static data flow architecture based on research done by Jack B. Dennis at MIT. To improve understanding of this architecture, a static data flow simulator, written in Pascal, has been implemented for use on a Cray X-MP/48. A matrix multiply and a two-dimensional fast Fourier transform (FFT), two algorithms used in CFD work at Ames, have been run on the simulator. Execution times can vary by a factor of more than 2 depending on the partitioning method used to assign instructions to processing elements. Service time for matching tokens has proved to be a major bottleneck. Loop control and array address calculation overhead can double the execution time. The best sustained MFLOPS rates were less than 50% of the maximum capability of the machine

A bibliography on parallel and vector numerical algorithms

This is a bibliography of numerical methods. It also includes a number of other references on machine architecture, programming language, and other topics of interest to scientific computing. Certain conference proceedings and anthologies which have been published in book form are listed also

Solution of partial differential equations on vector and parallel computers

The present status of numerical methods for partial differential equations on vector and parallel computers was reviewed. The relevant aspects of these computers are discussed and a brief review of their development is included, with particular attention paid to those characteristics that influence algorithm selection. Both direct and iterative methods are given for elliptic equations as well as explicit and implicit methods for initial boundary value problems. The intent is to point out attractive methods as well as areas where this class of computer architecture cannot be fully utilized because of either hardware restrictions or the lack of adequate algorithms. Application areas utilizing these computers are briefly discussed

Estudo do relaxamento da condição de dupla entrada em uma arquitetura hibrida

Orientador: Arthur João CattoArquivo incompleto - falta página 118Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Matematica, Estatistica e Ciencia da ComputaçãoResumo: As arquiteturas híbridas resultantes da junção das melhores características dos modelos von Neumann e de fluxo de dados formam uma nova classe de sistemas .paralelos de alto desempenho. A máquina MX é uma proposta preliminar e abstrata de uma arquitetura híbrida que utiliza a técnica de Fluxo de Dados para desmembrar programas em blocos de instruções limitados ao máximo de dois operandos de entrada. Este trabalho apresenta uma análise de técnicas mais eficientes de desmembramento para arquiteturas híbridas cujo modelo de execução não impõe restrições quanto ao número de operandos de entrada de um bloco de instruções. A escalabilidade da máquina MX e a influência do tamanho do bloco de instruções no seu desempenho sustentam a proposta de relaxamento da restrição da dupla entrada de um bloco de instruções, com o propósito de aumentar o desempenho da MX, conservando as suas características arquiteturais.Abstract: Hybrid architectures which result from joining the best features of the von Neumann and data flow computational models give rise to a new class of high performance parallel systems. The MX machine is a preliminary and abstract hybrid architecture proposal which resorts to data flow techniques for partitioning programs into instruction streams which are limited to two entry operands. This thesis presents an analysis of more efficient partitioning techniques for hybrid architectures whose execution model does not restrict the number of entry operands in an instruction stream. The scalability of the MX machine and the influence of the instruction stream size on its performance support a proposal for waiving the double entry limit to an instruction stream, aiming at increasing the performance of the MX machine, without altering its architectural characteristics.MestradoMestre em Ciência da Computaçã