System integration and verification of GNSS baseband processor

Satellite navigation, in the last three decades, has seen an evolution bringing up entirely new systems (Galileo) and modernization of existing systems (Global Positioning System). These systems have now changed the environment of the receiver design resulting in the development of Global Navigation Satellite System (GNSS) with new signal processing algorithms. GNSS receiver receives the signals from a GNSS satellite constellation, digitally processes them and provides position, velocity and time. Hardware GNSS receivers have good efficiency, good computational load and low power consumption. Such a hardware GNSS receiver is presented here. GNSS Receiver Reference Design is a fully functional L1 only GNSS receiver design. The main objective for this design is to make fully open access architecture (HW + SW) available to industry partners and researchers for development of GNSS and GNSSenhanced devices, for investigating current GNSS receivers and receiver algorithms and upcoming GNSS receiver standards. Baseband processing generates pre-processed data from received signals. It comprises digital signal processing executed by custom hardware (baseband system) and control processing implemented by a soft-core processor (COFFEE RISC core). The baseband system component performs acquisition and tracking of 6 channels. It currently provides only GPS coarse/acquisition (C/A) code. It is implemented by Field Programmable Gate Array (FPGA) logic, supported by hardware macros. The baseband system and the processor are to be integrated efficiently to manage the receiver activity. The integration is achieved by designing an interface that is compatible with the standard bus architecture. The interface is a shared system bus that contains a register database. The interface is implemented in RTL and verified in functional simulations. In this thesis, another objective of verifying the baseband system is achieved by targeting the maximum code coverage. The results show that this improves the quality of verification and provides good confidence in the design. The coverage numbers prove that the verification is extensive, close to 100%. Finally, synthesis is also needed for verifying the design implementation on gate level. Since the baseband system included many of Xilinx based models, both the subsystems are synthesized on Xilinx Virtex-II Pro platform. The synthesis results provide information on the on-chip area consumption

System integration and verification of GNSS baseband processor

Satellite navigation, in the last three decades, has seen an evolution bringing up entirely new systems (Galileo) and modernization of existing systems (Global Positioning System). These systems have now changed the environment of the receiver design resulting in the development of Global Navigation Satellite System (GNSS) with new signal processing algorithms. GNSS receiver receives the signals from a GNSS satellite constellation, digitally processes them and provides position, velocity and time. Hardware GNSS receivers have good efficiency, good computational load and low power consumption. Such a hardware GNSS receiver is presented here. GNSS Receiver Reference Design is a fully functional L1 only GNSS receiver design. The main objective for this design is to make fully open access architecture (HW + SW) available to industry partners and researchers for development of GNSS and GNSSenhanced devices, for investigating current GNSS receivers and receiver algorithms and upcoming GNSS receiver standards. Baseband processing generates pre-processed data from received signals. It comprises digital signal processing executed by custom hardware (baseband system) and control processing implemented by a soft-core processor (COFFEE RISC core). The baseband system component performs acquisition and tracking of 6 channels. It currently provides only GPS coarse/acquisition (C/A) code. It is implemented by Field Programmable Gate Array (FPGA) logic, supported by hardware macros. The baseband system and the processor are to be integrated efficiently to manage the receiver activity. The integration is achieved by designing an interface that is compatible with the standard bus architecture. The interface is a shared system bus that contains a register database. The interface is implemented in RTL and verified in functional simulations. In this thesis, another objective of verifying the baseband system is achieved by targeting the maximum code coverage. The results show that this improves the quality of verification and provides good confidence in the design. The coverage numbers prove that the verification is extensive, close to 100%. Finally, synthesis is also needed for verifying the design implementation on gate level. Since the baseband system included many of Xilinx based models, both the subsystems are synthesized on Xilinx Virtex-II Pro platform. The synthesis results provide information on the on-chip area consumption