LDPC decoder architecture for DVB-S2 and DVB-S2X standards

International audienceA particular type of conflict due to multiple-diagonal sub-matrices in the DVB-S2 parity-check matrices is known to complicate the implementation of the layered decoder architecture. The new matrices proposed in DVB-S2X no longer use such sub-matrices. For implementing a decoder compliant both with DVB-S2 and DVB-S2X, we propose an elegant solution which overcomes this conflicts relying on an efficient write disable of the memories, allowing a straightforward implementation of layered LDPC decoders. The complexity and latency are further reduced by eliminating one barrel shifter. Compared with the existing solutions, complexity is reduced without performance degradation. Keywords—Low-Density Parity-Check (LDPC) code, memory conflict, layered decoder, DVB-S2, DVB-S2X

Probabilistic Shaping for Asymmetric Channels and Low-Density Parity-Check Codes

An algorithm is proposed to encode low-density parity-check (LDPC) codes into codewords with a non-uniform distribution. This enables power-efficient signalling for asymmetric channels. We show gains of 0.9 dB for additive white Gaussian noise (AWGN) channels with on-off keying modulation using 5G LDPC codes.Comment: submitted to ISTC 202

An efficient reconfigurable code rate cooperative low-density parity check codes for gigabits wide code encoder/decoder operations

In recent days, extensive digital communication process has been performed. Due to this phenomenon, a proper maintenance of authentication, communication without any overhead such as signal attenuation code rate fluctuations during digital communication process can be minimized and optimized by adopting parallel encoder and decoder operations. To overcome the above-mentioned drawbacks by using proposed reconfigurable code rate cooperative (RCRC) and low-density parity check (LDPC) method. The proposed RCRC-LDPC is capable to operate over gigabits/sec data and it effectively performs linear encoding, dual diagonal form, widens the range of code rate and optimal degree distribution of LDPC mother code. The proposed method optimize the transmission rate and it is capable to operate on 0.98 code rate. It is the highest upper bounded code rate as compared to the existing methods. The proposed method optimizes the transmission rate and is capable to operate on a 0.98 code rate. It is the highest upper bounded code rate as compared to the existing methods. the proposed method's implementation has been carried out using MATLAB and as per the simulation result, the proposed method is capable of reaching a throughput efficiency greater than 8.2 (1.9) gigabits per second with a clock frequency of 160 MHz

VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes

A low-density parity-check (LDPC) decoder architecture that supports variable block sizes and multiple code rates is presented. The proposed architecture is based on the structured quasi-cyclic (QC-LDPC) codes whose performance compares favorably with that of randomly constructed LDPC codes for short to moderate block sizes. The main contribution of this work is to address the variable block-size and multirate decoder hardware complexity that stems from the irregular LDPC codes. The overall decoder, which was synthesized, placed and routed on TSMC 0.13-micron CMOS technology with a core area of 4.5 square millimeters, supports variable code lengths from 360 to 4200 bits and multiple code rates between 1/4 and 9/10. The average throughput can achieve 1 Gbps at 2.2 dB SNR.NokiaNational Science Foundatio

Scalable and Low Power LDPC Decoder Design Using High Level Algorithmic Synthesis

This paper presents a scalable and low power low-density parity-check (LDPC) decoder design for the next generation wireless handset SoC. The methodology is based on high level synthesis: PICO (program-in chip-out) tool was used to produce efficient RTL directly from a sequential untimed C algorithm. We propose two parallel LDPC decoder architectures: (1) per-layer decoding architecture with scalable parallelism, and (2) multi-layer pipelined decoding architecture to achieve higher throughput. Based on the PICO technology, we have implemented a two-layer pipelined decoder on a TSMC 65nm 0.9V 8-metal layer CMOS technology with a core area of 1.2 mm2. The maximum achievable throughput is 415 Mbps when operating at 400 MHz clock frequency and the estimated peak power consumption is 180 mW.NokiaNokia Siemens Networks (NSN)XilinxNational Science Foundatio

Design and Evaluation of the Efficiency of Channel Coding LDPC Codes for 5G Information Technology

This paper proposes a result of an investigation of a topical problem and the development of models for efficient coding in information networks based on codes with a low density of parity check. The main advantage of the technique is the presented recommendations for choosing a signal-code construction is carried out taking into account the code rate and the number of iterations decoding for envisaging the defined noise immunity indices. The noise immunity of signal-code constructions based on low-density codes has been increased by combining them with multi position digital modulation. This solution eventually allowed to develop a strategy for decoder designing of such codes and to optimize the code structure for a specific information network. To test the effectiveness of the proposed method, MATLAB simulations are carried out under for various Information channels binary symmetric channel (BSC), a channel with additive white Gaussian noise (AWGN), binary asymmetric channel (BAC), asymmetric channel Z type. In addition, different code rates were used during the experiment. The study of signal-code constructions with differential modulation is presented. The efficiency of different decoding algorithms is investigated. The advantage of the obtained results over the known ones consists in determining the maximum noise immunity for the proposed codes. The energy gain was on the order of 6 dB, and an increase in the number of decoding iterations from 3 to 10 leads to a gain in coding energy of 5 dB. Envisaged that the results obtained can be very useful in the development of practical coding schemes in 5G networks

A Hardware Implementation for Code-based Post-quantum Asymmetric Cryptography

This paper presents a dedicated hardware implementation of the LEDAcrypt cryptosystem, which uses Quasi-Cyclic Low-Density Parity-Check codes and the Q decoder for the decryption function. The designed architecture is synthesized for both FPGA and ASIC technologies, featuring an intrinsic scalability over a wide range of parallelism degrees, which makes it possible to target multiple application scenarios, with different trade-offs between decryption latency and implementation complexity. The proposed system achieves a large speed-up over both software execution and a previous hardware implementation, with a the decryption latency as low as 3.16 ms for the FPGA version, and 1.2 ms when synthesized for a 65 nm CMOS technology