Scalable Energy-Recovery Architectures.

Energy efficiency is a critical challenge for today's integrated circuits, especially for high-end digital signal processing and communications that require both high throughput and low energy dissipation for extended battery life. Charge-recovery logic recovers and reuses charge using inductive elements and has the potential to achieve order-of-magnitude improvement in energy efficiency while maintaining high performance. However, the lack of large-scale high-speed silicon demonstrations and inductor area overheads are two major concerns. This dissertation focuses on scalable charge-recovery designs. We present a semi-automated design flow to enable the design of large-scale charge-recovery chips. We also present a new architecture that uses in-package inductors, eliminating the area overheads caused by the use of integrated inductors in high-performance charge-recovery chips. To demonstrate our semi-automated flow, which uses custom-designed standard-cell-like dynamic cells, we have designed a 576-bit charge-recovery low-density parity-check (LDPC) decoder chip. Functioning correctly at clock speeds above 1 GHz, this prototype is the first-ever demonstration of a GHz-speed charge-recovery chip of significant complexity. In terms of energy consumption, this chip improves over recent state-of-the-art LDPCs by at least 1.3 times with comparable or better area efficiency. To demonstrate our architecture for eliminating inductor overheads, we have designed a charge-recovery LDPC decoder chip with in-package inductors. This test-chip has been fabricated in a 65nm CMOS flip-chip process. A custom 6-layer FC-BGA package substrate has been designed with 16 inductors embedded in the fifth layer of the package substrate, yielding higher Q and significantly improving area efficiency and energy efficiency compared to their on-chip counterparts. From measurements, this chip achieves at least 2.3 times lower energy consumption with better area efficiency over state-of-the-art published designs.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/116653/1/terryou_1.pd

Engineering biocomputers in mammalian cells

Endowing cells with enhanced decision-making capacities is essential for creating smarter therapeutics and for dissecting phenotypes. Implementation of synthetic gene circuits affords a means for enhanced cellular control and genetic processing; however, genetic circuits for mammalian cells often require extensive fine-tuning to perform as intended. Here, a robust, general, and scalable system, called 'Boolean logic and arithmetic through DNA excision' (BLADE) is presented that is used to engineer genetic circuits with multiple inputs and outputs in mammalian cells with minimal optimization. The reliability of BLADE arises from its reliance on site-specific recombinases that regulate genes under the control of a single promoter that integrates circuit signals on a single transcriptional layer. Using BLADE, >100 circuits were tested in human embryonic kidney and Jurkat T cells and a quantitative metric was used to evaluate their performance. The circuits include a 3-input, two-output full adder; a 6-input, one-output Boolean logic look-up table; and circuits that incorporate CRISPR–Cas9 to regulate endogenous genes. Moreover, a large library of over 15 small-molecule, light and temperature-inducible recombinases has been established for fine-tuned control. BLADE enables execution of sophisticated cellular computation in mammalian cells, with applications in cell and tissue engineering