Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation

Noise, as well as area, delay, and power, is one of the most important concerns in the design of deep sub-micron ICs. Currently existing algorithms can not handle simultaneous switching conditions of signals for noise minimization. In this paper, we model not only physical coupling capacitance, but also simultaneous switching behavior for noise optimization. Based on Lagrangian relaxation, we present an algorithm that can optimally solve the simultaneous noise, area, delay, and power optimization problem by sizing circuit components. Our algorithm, with linear memory requirement overall and linear runtime per iteration, is very effective and efficient. For example, for a circuit of 6144 wires and 3512 gates, our algorithm solves the simultaneous optimization problem using only 2.1 MB memory and 47 minute runtime to achieve the precision of within 1% error on a SUN UltraSPARC-I workstation

Early Estimation Of The Impact Of Delay Due To Coupling Capacitance In VSLI Circuits

University of Minnesota M.S.E.E. thesis.May 2019. Major: Electrical/Computer Engineering. Advisor: Sachin Sapatnekar. 1 computer file (PDF); vii, 54 pages.Coupling capacitance is becoming increasingly problematic at the more advanced technology nodes and affects the timing and sign-off timeline of integrated circuits (ICs). As the coupling capacitance information is only available after the detailed routing phase, it can be a difficult task to make any major changes post detailed routing towards fixing issues caused by coupling effects that were unaccounted for. The goal of the project is to come up with an estimate of coupling capacitance for a given net before the detailed routing phase with the help of congestion maps. This information can be fed back to the detailed router which can help avoid routes that are susceptible to heavy coupling effects. The first part of this thesis explains why beforehand knowledge of a net’s coupling capacitance is crucial for a timely tape-out. This thesis revisits the Elmore delay model and extends the analysis to coupled RC structures. The notion of considering the coupling capacitance as a random variable is described to model the uncertainties that are introduced into the delay analysis which is performed ahead in time. The second part of this thesis illustrates how congestion analysis can provide valuable information about the severity of coupling effects. A method for the expedited extraction of estimated parasitics using congestion maps and global router solutions is presented. Modification to existing driving-point analysis techniques is suggested to accommodate coupled RC structures with probabilistic coupling capacitance. The last part of this thesis compares the delay metrics obtained from an open-source timing analyzer with the delay metrics obtained through methods described in this thesis for a given net

Track Assignment Considering Crosstalk-Induced Performance Degradation

Track assignment is a critical step between global routing and detailed routing in modern VLSI chip designs. It greatly affects some very important design characteristics, such as routability, via usage and timing performance. Crosstalk, which is largely decided by wire adjacency, has significant impact on interconnect delay and circuit performance. Therefore, the amount of crosstalk should be restrained in order to satisfy timing constraints. In this work, a track assignment approach is proposed to control crosstalk-induced performance degradation. The problem is formulated as a Traveling Salesman Problem (TSP) and solved by a graph-based heuristic. The proposed approach is implemented and tested on benchmark circuits from the ISPD2011 contest and the experimental results are quite promising