A Hybrid Folded Cascode OP Amp with Positive Feedback And DSB Circuit

A novel high-speed folded-cascode OP Amp with positive feedback and a dynamic switching bias circuit, which increases the speed and lower the power dissipation has been proposed . The proposed Op-Amp was designed in a standard 0.18µm CMOS technology and simulation is performed using tanner EDA tool. Simulation results show a considerable increase in speed, increased output voltage swing and low power consumption for the presented Op-Amp. This proposed circuit overcomes some drawbacks of the conventional circuit in which only positive feedback is used. DOI: 10.17762/ijritcc2321-8169.150610

Performance enhancement techniques for operational amplifiers

Operational amplifiers (op amps) are one of the most fundamental and widely used building blocks for analog and mixed-signal circuits and systems. As transistors’ feature size scales down in the deep submicron process, the short channel effects, high leakage current and reduced supply voltages make the design of op amps more challenging. In this dissertation, we present several methods to improve op amps’ DC gain, slew rate, power efficiency and current utilization efficiency (CUE). A basic requirement for an op amp is high DC gain especially for high precision applications. We introduce a method to robustly improve op amps’ DC gain with negligible power and area overhead. The new DC gain enhancement method can be implemented based on the source degeneration circuit (SDC) or the flipped voltage attenuator (FVA). Compared to the FVA-based technique, the SDC-based technique is more suitable for those CMOS processes whose transistors’ threshold voltages are too low for the transistors in the FVA to work in weak or strong inversion regions. Otherwise, the FVA-based technique is recommended as this technique is more robust to devices’ random mismatch. A prototype op amp with the FVA-based technique is designed and fabricated in the IBM130nm process. The measurement and simulation results of the prototype verify that the technique largely enhances an op amp’s DC and is very robust over process, voltage and temperature variations. Another important op amp requirement is high slew rate. In this regard, we introduce a method that greatly improves an op amp’s slew rate while still preserving its small signal performance by a well-defined turn-on condition. The performance of the introduced method is discussed in comparison with an existing adaptive biasing method that was widely used to enhance slew rate. The introduced method excels in several aspects. First, unlike the adaptive biasing method which degrades an op amp’ linearity, the introduced method is able to enhance linearity. Second, the proposed method improves an op amp’s slew rate by 2320% (vs. 780% by the adaptive method) with the power and area overhead of 2% and 1.2% (vs. 15% and 35% by the adaptive method). In addition, the proposed method improves the op amp’s total harmonic distortion (THD) by 6dB but the adaptive method degrades the THD by 12dB. The ability to drive large capacitive loads is becoming critical for op amps in emerging applications such as liquid crystal display drivers. In this regard, we introduce a power efficient design of op amps that can drive large capacitive loads. The proposed method decouples the large and small signal performance, eliminates current waste in the preamp stages’ load circuits, and is not sensitive to devices’ random mismatches. Compared to the state-of-the-art methods, our design prototype in a CMOS 180nm process shows largely improved small and large signal figure of merits, equivalent to largely improved power efficiency for given small and large signal performance specifications. Folded cascode amplifier (FCA) is a commonly used architecture for designing op amps, but a significant portion of supply current is wasted in the cascode stage. This not only reduces the current utilization efficiency (CUE), defined as the ratio of an FCA’s tail current to its total supply current, but also degrades the FCA’s gain, noise and offset. In this regard, we introduce a method to dramatically reduce a FCA’s cascode stage current without degrading the FCA’s settling performance. Compared to the existing methods, the proposed method effectively improves not only the CUE but also the settling performance of op amps. Lastly, a prototype FCA, with the proposed performance enhancement techniques of gain, slew rate and CUE, is designed to demonstrate the compatibility of these techniques

Amplifier performance enhancement methods using positive feedback techniques

The dramatic growth in the hi-tech sector of consumer market has created many unprecedented challenges in the area of integrated circuits. The present and future communication and entertainment systems including high speed cable and DSL modems, broadband wired and wireless systems, and high definition visual products require very fast and high accuracy amplifiers, data converters and filters. Analog design in the new digital CMOS submicron processes is becoming an economical necessity in the industry. The task of building fast Op-Amp with very high DC-gain is already a very difficult problem, and this task has become more difficult using these new submicron digital processes, where traditional gain enhancement techniques are loosing their ability to deliver amplifiers with sufficient gain. In this work three new methods of implementing the internal positive-feedback to build very high DC-gain amplifiers with very low gain sensitivity to signal swings are presented. Amplifiers proposed in the first method have very high current-controlled gain. A DC gain larger than 100dB is possible without limiting the speed of the amplifier. Amplifiers proposed in the second method exhibit both enhanced speed, i.e., unity gain frequency, and enhanced gain. Amplifiers proposed in the third method have self-adjusting gain without extra control block. An implementation of a 3 bit multiplying DAC in a 9-bit 165MS/s pipeline ADC built in a 1.8V, 0.21mu digital CMOS process using one of the proposed amplifiers is described. Test results show high gain with very fast settling

Slew-rate enhancement and trojan state avoiding for fully-differential operational amplifier

Operational amplifiers are fundamental building blocks in modern analog and mixed-signal systems such as data converters, switched-capacitor circuits, and filters. The fully-differential structure is extensively used in these applications because of its improved dynamic performance with respect to such aspects as signal-to-noise ratio (SNR) and total harmonic distortion (THD) when compared to its single-ended counterpart. In some of these applications, the fully-differential amplifier is required to have fast transient settling time without slew-rate limitations. Power consumption also must be taken into consideration because low power consumption can significantly reduce a battery\u27s weight and size, and extend its life-time. A Class A amplifier is a difficult configuration in which to conciliate all these requirements, since its fixed bias current can limit its maximum output current. To simultaneously meet both slew-rate and power consumption requirements, several slew-rate enhancement (SRE) techniques have been proposed in the literature, but all of them are either incompatible with the low voltage operation or exhibit either degradation in linearity or increase in circuit complexity. This thesis presents a simple SRE technique, efficient in both power and area usage, improve the slew rate while overcoming the drawbacks of state-of-the-art SRE techniques. In this work, several existing SRE techniques are discussed, and their advantages and disadvantages are identified. The proposed SRE technique is based on excess transient detection and feedback. A transient signal can be detected at the internal nodes of amplifier. Once the detected transient signal is found to be larger than a pre-defined turn-on value, the excess transient signal can be instantaneously amplified to turn on a dynamic current source and feed it back to the amplifier for current boosting. This pre-defined turn-on voltage results in a SRE circuit being solidly off during quiescent state. Small-signal performance and linearity of the original amplifier can be thus well preserved. Thanks to this excess transient feedback concept, the implementation is much simpler than that of previously reported methods, and the static power overhead is also very small. Using the proposed SRE method, a fully-differential folded-cascode two-stage op-amp has been designed and fabricated using IBM 130nm process. This amplifier is designed to validate the proposed method of improving an amplifier\u27s input-stage slew-rate. If the tail current doubles during slewing, the simulation result indicates that, at all corners, with temperature from 0°C to 60°C the average slew-rate can be enhanced by a factor of 2.6 and the 1% settling time after a large input step is reduced by 30% compared to the vales without using SRE. Any further increment in the tail transient current can further increase the internal slew rate and eventually make it equal to the output-stage slew-rate. It is well-known that self-stabilized circuits, such as current, voltage and frequency references, are vulnerable to a problem of multiple operating points; this is also known as the start-up problem. An op-amp can suffer from the same problem when performance enhancement feedback is being used. In particular, a slew rate enhancement circuit (SRE) can be used to provide performance enhancement in low-power high-speed op-amp design. For such circuits, a systematic method for detecting and removal of Trojan states is presented. Using a design example and simulation results, it is demonstrated that the proposed method can effectively remove a Trojan state in an op-amp without degrading the improved slew-rate

A 90 dB, 85 MHz operational transconductance amplifier (OTA) using gain boosting technique

Gain and speed are the two most important parameters of an amplifier. Optimizing an amplifier for both of these parameters leads to contradicting demands. Various architectures have been reported to obtain high gain from the circuits. Cascode circuits are widely used in circuit design at places where high gain and high output impedances are required. Different architectures like triple cascode topology, dynamic biasing and a positive feedback amplifier have been used to obtain high gains. These architectures have been compared in this thesis along with drawbacks and advantages of each

Strategies for enhancing DC gain and settling performance of amplifiers

The operational amplifier (op amp) is one of the most widely used and important building blocks in analog circuit design. High gain and high speed are two important properties of op amps because they determine the settling behavior of the op amps. As supply voltages decrease, the realization of high gain amplifiers with large Gain-Bandwidth-Products (GBW) has become challenging. The major focus in this dissertation is on the negative output impedance gain enhancement technique. The negative impedance gain enhancement technique offers potential for achieving very high gain and energy-efficient fast settling and is low-voltage compatible. Misconceptions that have limited the practical adoption of this gain enhancement technique are discussed. A new negative conductance gain enhancement technique was proposed. The proposed circuit generates a negative conductance with matching requirements for achieving very high DC gain that are less stringent than those for existing -g m gain enhancement schemes. The proposed circuit has potential for precise digital control of a very large DC gain. A prototype fully differential CMOS operational amplifier was designed and fabricated based on the proposed gain enhancement technique. Experimental results which showed a DC gain of 85dB and an output swing of 876mVp-p validated the fundamental performance characteristics of this technique. In a separate section, a new amplifier architecture with bandpass feedforward compensation is presented. It is shown that a bandpass feedforward path can be used to substantially extend the unity-gain-frequency of an operational amplifier. Simulation results predict significant improvements in rise time and settling performance and show that the bandpass compensation scheme is reasonably robust. In the final section, a new technique for asynchronous data recovery based upon using a delay line in the incoming data path is introduced. The proposed data recovery system is well suited for tight tolerance channels and coding systems supporting standards that limit the maximum number of consecutive 0\u27s and 1\u27s in a data stream. This system does not require clock recovery, suffers no loss of data during acquisition, has a reduced sensitivity to jitter in the incoming data and does not exhibit jitter enhancement associated with VCO tracking in a PLL

A Silicon Carbide Power Management Solution for High Temperature Applications

The increasing demand for discrete power devices capable of operating in high temperature and high voltage applications has spurred on the research of semiconductor materials with the potential of breaking through the limitations of traditional silicon. Gallium nitride (GaN) and silicon carbide (SiC), both of which are wide bandgap materials, have garnered the attention of researchers and gradually gained market share. Although these wide bandgap power devices enable more ambitious commercial applications compared to their silicon-based counterparts, reaching their potential is contingent upon developing integrated circuits (ICs) capable of operating in similar environments. The foundation of any electrical system is the ability to efficiently condition and supply power. The work presented in this thesis explores integrated SiC power management solutions in the form of linear regulators and switched capacitor converters. While switched-mode converters provide high efficiency, the requirement of an inductor hinders the development of a compact, integrated solution that can endure harsh operating environments. Although the primary research motivation for wide bandgap ICs has been to provide control and protection circuitry for power devices, the circuitry designed in this work can be incorporated in stand-alone applications as well. Battery or generator powered data acquisition systems targeted towards monitoring industrial machinery is one potential usage scenario

Design methodology for general enhancement of a single-stage self-compensated folded-cascode operational transconductance amplifiers in 65 nm CMOS process

The problems resulting from the use of nano-MOSFETs in the design of operational trans-conductance amplifiers (OTAs) lead to an urgent need for new design techniques to produce high-performance metrics OTAs suitable for very high-frequency applications. In this paper, the enhancement techniques and design equations for the proposed single-stage folded-cascode operational trans-conductance amplifiers (FCOTA) are presented for the enhancement of its various performance metrics. The proposed single-stage FCOTA adopts the folded-cascode (FC) current sources with cascode current mirrors (CCMs) load. Using 65 nm complementary metal-oxide semiconductor (CMOS) process from predictive technology model (PTM), the HSPICE2019-based simulation results show that the designed single-stage FCOTA can achieve a high open-loop differential-mode DC voltage gain of 65.64 dB, very high unity-gain bandwidth of 263 MHz, very high stability with phase-margin of 73°, low power dissipation of 0.97 mW, very low DC input-offset voltage of 0.14 uV, high swing-output voltages from −0.97 to 0.91 V, very low equivalent input-referred noise of 15.8 nV/Hz, very high common-mode rejection ratio of 190.64 dB, very high positive/negative slew-rates of 157.5/58.3 V⁄us, very fast settling-time of 5.1 ns, high extension input common-mode range voltages from −0.44to 1 V, and high positive/negative power-supply rejection ratios of 75.5/68.8 dB. The values of the small/large-signal figures-of-merits (s) are the highest when compared to other reported FCOTAs in the literature

Novel approaches in current-feedback operational amplifier design

The aim of this research programme was to design and develop a novel bipolar junction transistor Current Feedback Operational Amplifier (CFOA) with a good Common-Mode Rejection Ratio (CMRR), suitable for radio frequency (RF) applications. This research focused on investigation of the established CFOA with the emphases of improving CMRR, bandwidth, Voltage-Offset and Slew-rate performance. The majority of the results of this work have been reported by the author in references [11 to [6]. Initially a thorough analysis of the conventional CFOA was undertaken to provide an in depth understanding of the amplifier's operation, and this work revealed that the main shortcomings of the CFOA are in the design of the input stage. This initial study focussed on establishing reasons for the poor DC offset-voltage performance and CMRR and confirmed that these designs have inherently poor performance in these two elements. The analysis was carried out using both theoretical modelling and computer simulation. Using this analysis of the conventional CFOA as a benchmark, various novel circuit techniques were investigated. Several new input circuits for the CFOA were proposed with respect to improving the three previously mentioned key characteristics, viz., CMRR, offset voltage, and slew-rate. The first technique explored is based on floating the entire input stage of the CFOA which yielded significant improvements in CMRR, Offset-Voltage and bandwidth, and the results of this workwere published in [11, [2], and P). Based on these initial findings a second major development was undertaken. This time a bootstrapping technique was employed to key sections of the input stage, leading to new, simplified input circuit topology. This development leads to low DC offset voltage, wide bandwidth and high CNIRR, as well as improved gain accuracy, and was published by the author in [4,5]. A logical approach to the different input stage architectures examined by the author resulted in identification of a hierarchy of 6 different input CFOA circuit designs and a comparative study was undertaken showing their relative performance in respect of CMRR, Offset-Voltage and Slew-rate. This work was presented by the author, [6]