An Effective EMTR-Based High-Impedance Fault Location Method for Transmission Lines

This paper summarizes the electromagnetic time reversal (EMTR) technique for fault location, and further numerically validates its effectiveness when the fault impedance is negligible. In addition, a specific EMTR model considering the fault impedance is derived, and the correctness of the model derivation is verified by various calculation methods. Based on this, we found that when the fault impedance is large, the existing EMTR methods might fail to accurately locate the fault. We propose an EMTR method that improves the location effect of high-impedance faults by injecting double-ended signals simultaneously. Theoretical calculations show that this method can achieve accurate location for high-impedance faults. To further illustrate the effectiveness, the proposed method is compared with the existing EMTR methods and the most commonly used traveling wave-based method using wavelet transform. The simulation results show that the proposed double-ended EMTR method can effectively locate high-impedance faults, and it is more robust against synchronization errors compared to the traveling wave method. In addition, the proposed method does not require the knowledge or the a priori guess of the unknown fault impedance

A novel fault location method for a cross-bonded hv cable system based on sheath current monitoring

In order to improve the practice in the operation and maintenance of high voltage (HV) cables, this paper proposes a fault location method based on the monitoring of cable sheath currents for use in cross-bonded HV cable systems. This method first analyzes the power–frequency component of the sheath current, which can be acquired at cable terminals and cable link boxes, using a Fast Fourier Transform (FFT). The cable segment where a fault occurs can be localized by the phase difference between the sheath currents at the two ends of the cable segment, because current would flow in the opposite direction towards the two ends of the cable segment with fault. Conversely, in other healthy cable segments of the same circuit, sheath currents would flow in the same direction. The exact fault position can then be located via electromagnetic time reversal (EMTR) analysis of the fault transients of the sheath current. The sheath currents have been simulated and analyzed by assuming a single-phase short-circuit fault to occur in every cable segment of a selected cross-bonded high voltage cable circuit. The sheath current monitoring system has been implemented in a 110 kV cable circuit in China. Results indicate that the proposed method is feasible and effective in location of HV cable short circuit faults

Formal Modeling of Connectionism using Concurrency Theory, an Approach Based on Automata and Model Checking

This paper illustrates a framework for applying formal methods techniques, which are symbolic in nature, to specifying and verifying neural networks, which are sub-symbolic in nature. The paper describes a communicating automata [Bowman & Gomez, 2006] model of neural networks. We also implement the model using timed automata [Alur & Dill, 1994] and then undertake a verification of these models using the model checker Uppaal [Pettersson, 2000] in order to evaluate the performance of learning algorithms. This paper also presents discussion of a number of broad issues concerning cognitive neuroscience and the debate as to whether symbolic processing or connectionism is a suitable representation of cognitive systems. Additionally, the issue of integrating symbolic techniques, such as formal methods, with complex neural networks is discussed. We then argue that symbolic verifications may give theoretically well-founded ways to evaluate and justify neural learning systems in the field of both theoretical research and real world applications

Pruned Bit-Reversal Permutations: Mathematical Characterization, Fast Algorithms and Architectures

A mathematical characterization of serially-pruned permutations (SPPs) employed in variable-length permuters and their associated fast pruning algorithms and architectures are proposed. Permuters are used in many signal processing systems for shuffling data and in communication systems as an adjunct to coding for error correction. Typically only a small set of discrete permuter lengths are supported. Serial pruning is a simple technique to alter the length of a permutation to support a wider range of lengths, but results in a serial processing bottleneck. In this paper, parallelizing SPPs is formulated in terms of recursively computing sums involving integer floor and related functions using integer operations, in a fashion analogous to evaluating Dedekind sums. A mathematical treatment for bit-reversal permutations (BRPs) is presented, and closed-form expressions for BRP statistics are derived. It is shown that BRP sequences have weak correlation properties. A new statistic called permutation inliers that characterizes the pruning gap of pruned interleavers is proposed. Using this statistic, a recursive algorithm that computes the minimum inliers count of a pruned BR interleaver (PBRI) in logarithmic time complexity is presented. This algorithm enables parallelizing a serial PBRI algorithm by any desired parallelism factor by computing the pruning gap in lookahead rather than a serial fashion, resulting in significant reduction in interleaving latency and memory overhead. Extensions to 2-D block and stream interleavers, as well as applications to pruned fast Fourier transforms and LTE turbo interleavers, are also presented. Moreover, hardware-efficient architectures for the proposed algorithms are developed. Simulation results demonstrate 3 to 4 orders of magnitude improvement in interleaving time compared to existing approaches.Comment: 31 page