Limits on Fundamental Limits to Computation

An indispensable part of our lives, computing has also become essential to industries and governments. Steady improvements in computer hardware have been supported by periodic doubling of transistor densities in integrated circuits over the last fifty years. Such Moore scaling now requires increasingly heroic efforts, stimulating research in alternative hardware and stirring controversy. To help evaluate emerging technologies and enrich our understanding of integrated-circuit scaling, we review fundamental limits to computation: in manufacturing, energy, physical space, design and verification effort, and algorithms. To outline what is achievable in principle and in practice, we recall how some limits were circumvented, compare loose and tight limits. We also point out that engineering difficulties encountered by emerging technologies may indicate yet-unknown limits.Comment: 15 pages, 4 figures, 1 tabl

Portable low profile antenna at X-band

An antenna which has been conceived as a portable system for satellite communications based on the recommendations ITU-R S.580-6 and ITU-R S.465-5 for small antennas, i.e., with a diameter lower than 50 wavelengths, is introduced. It is a planar and a compact structure with a size of 40×40×2 cm. The antenna is formed by an array of 256 printed elements covering a large bandwidth (14.7%) at X-Band with a VSWR of 1.4:1. The specification includes transmission (Tx) and reception (Rx) bands simultaneously. The printed antenna has a radiation pattern with a 3dB beamwidth of 5°, over a 31dBi gain, and a dual and an interchangeable circular polarization

Chameleon: A Hybrid Secure Computation Framework for Machine Learning Applications

We present Chameleon, a novel hybrid (mixed-protocol) framework for secure function evaluation (SFE) which enables two parties to jointly compute a function without disclosing their private inputs. Chameleon combines the best aspects of generic SFE protocols with the ones that are based upon additive secret sharing. In particular, the framework performs linear operations in the ring $\mathbb{Z}_{2^l}$ using additively secret shared values and nonlinear operations using Yao's Garbled Circuits or the Goldreich-Micali-Wigderson protocol. Chameleon departs from the common assumption of additive or linear secret sharing models where three or more parties need to communicate in the online phase: the framework allows two parties with private inputs to communicate in the online phase under the assumption of a third node generating correlated randomness in an offline phase. Almost all of the heavy cryptographic operations are precomputed in an offline phase which substantially reduces the communication overhead. Chameleon is both scalable and significantly more efficient than the ABY framework (NDSS'15) it is based on. Our framework supports signed fixed-point numbers. In particular, Chameleon's vector dot product of signed fixed-point numbers improves the efficiency of mining and classification of encrypted data for algorithms based upon heavy matrix multiplications. Our evaluation of Chameleon on a 5 layer convolutional deep neural network shows 133x and 4.2x faster executions than Microsoft CryptoNets (ICML'16) and MiniONN (CCS'17), respectively

Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

Multimedia applications are driving wireless network operators to add high-speed data services such as Edge (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing GSM network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above-mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-interoperability. This paper presents analog and digital base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) leve

Modular Planar Antenna at X-band for satellite communications

An antenna which has been conceived as a portable system for satellite communications based on the recommendations ITU-R S.580-6 [1] and ITU-R S.465-5 [2] for small antennas, i.e., with a diameter lower than 50 wavelengths, is introduced. It is a planar and a compact structure with a size of 40×40×2 cm. The antenna is formed by an array of 256 printed elements covering a large bandwidth (14.7%) at X-Band. The specification includes transmission (Tx) and reception (Rx) bands simultaneously. The printed antenna has a radiation pattern with a 3dB beamwidth of 5°, over a 31dBi gain, and a dual and an interchangeable circular polarizatio

Analysis of a Portable, One Hundred Ampere Pulse Test Current Microhmmeter

This report is an analysis of the Model RT-2 Microhmmeter which is a portable apparatus using a pulse current power source in the measurement of load resistances in the microhm range. The need for accurately measuring resistances in the microhm range is quite real for testing electrical power circuit breaker contact resistance. Both during acceptance checking within the manufacturing process and in the field for preventative maintenance, contact resistance must be accurately determined. Before the invention of the Model RT-2 Micrometer, no device existed which could accurately measure resistances in the microhm range that was readily transported by an unaided individual. The design of the Model RT-2 Microhmmeter is based on a specification set derived from user requirements, and ANSI C37.09. In addition, a weight limit of 25 pounds for the portable apparatus was imposed by the designer which included the weight of the self-contained power source. This paper suggests changes that will result in both weight and power consumption savings. A major change in the high current power supply circuit is suggested that will allow the microhmmeter to be a more versatile piece of test equipment. The Model RT-2 Microhmmeter is operational and has been successfully proven in the field. By using the portable microhmmeter, the reduction in the amount of time required to determine contact resistance can result in appreciable cost savings to the user

On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing

In this paper, a chip that performs real-time image convolutions with programmable kernels of arbitrary shape is presented. The chip is a first experimental prototype of reduced size to validate the implemented circuits and system level techniques. The convolution processing is based on the address–event-representation (AER) technique, which is a spike-based biologically inspired image and video representation technique that favors communication bandwidth for pixels with more information. As a first test prototype, a pixel array of 16x16 has been implemented with programmable kernel size of up to 16x16. The chip has been fabricated in a standard 0.35- m complimentary metal–oxide–semiconductor (CMOS) process. The technique also allows to process larger size images by assembling 2-D arrays of such chips. Pixel operation exploits low-power mixed analog–digital circuit techniques. Because of the low currents involved (down to nanoamperes or even picoamperes), an important amount of pixel area is devoted to mismatch calibration. The rest of the chip uses digital circuit techniques, both synchronous and asynchronous. The fabricated chip has been thoroughly tested, both at the pixel level and at the system level. Specific computer interfaces have been developed for generating AER streams from conventional computers and feeding them as inputs to the convolution chip, and for grabbing AER streams coming out of the convolution chip and storing and analyzing them on computers. Extensive experimental results are provided. At the end of this paper, we provide discussions and results on scaling up the approach for larger pixel arrays and multilayer cortical AER systems.Commission of the European Communities IST-2001-34124 (CAVIAR)Commission of the European Communities 216777 (NABAB)Ministerio de Educación y Ciencia TIC-2000-0406-P4Ministerio de Educación y Ciencia TIC-2003-08164-C03-01Ministerio de Educación y Ciencia TEC2006-11730-C03-01Junta de Andalucía TIC-141