A low-power cache system for high-performance processors

制度:新 ; 報告番号:甲3439号 ; 学位の種類:博士(工学) ; 授与年月日:12-Sep-11 ; 早大学位記番号:新576

Design of trace caches for high bandwidth instruction fetching

Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.Includes bibliographical references (leaves 60-63).by Michael Sung.M.Eng

Pollution Control Caching

POLLUTION CONTROL CACHING The bandwidth mismatch of today's high speed processors and standard DRAMS is between a factor of 10 to 50. From 1995 to the year 2000 this mismatch is expected to grow to three orders of magnitude, necessitating greater emphasis for on-chip caches. However, the cost of on-chip memory is largely a function of the chip area it requires. Today, these on-chip caches typically consume from 20% to 50% of the total chip area; clearly, only so much chip area can be devoted to caches. Any technique which can maintain memory performance and reduce chip area requirements is extremely important. In this paper we present two novel cache architectures called Pollution Control Caching (PCC) and Pollution Control Caching plus Victim Buffering (PCC+VB). We have used trace driven simulation to obtain miss ratio statistics on a variety of workloads for direct mapped, 2-Way, 4Way, 8-Way, PCC, and PCC+VB cache architectures. We developed analytical models of the expected clock cy..