Physical IC debug ─ backside approach and nanoscale challenge

Physical analysis for IC functionality in submicron technologies requires access through chip backside. Based upon typical global backside preparation with 50–100 µm moderate silicon thickness remaining, a state of the art of the analysis techniques available for this purpose is presented and evaluated for functional analysis and layout pattern resolution potential. A circuit edit technique valid for nano technology ICs, is also presented that is based upon the formation of local trenches using the bottom of Shallow Trench Isolation (STI) as endpoint for Focused Ion Beam (FIB) milling. As a derivative from this process, a locally ultra thin silicon device can be processed, creating a back surface as work bench for breakthrough applications of nanoscale analysis techniques to a fully functional circuit through chip backside. Several applications demonstrate the power and potential of this new approach

When Failure Analysis Meets Side-Channel Attacks

International audienceThe purpose of failure analysis is to locate the source of a defect in order to characterize it, using different techniques (laser stim- ulation, light emission, electromagnetic emission...). Moreover, the aim of vulnerability analysis, and particularly side-channel analysis, is to ob- serve and collect various leakages information of an integrated circuit (power consumption, electromagnetic emission ...) in order to extract sensitive data. Although these two activities appear to be distincted, they have in common the observation and extraction of information about a circuit behavior. The purpose of this paper is to explain how and why these activities should be combined. Firstly it is shown that the leak- age due to the light emitted during normal operation of a CMOS circuit can be used to set up an attack based on the DPA/DEMA technique. Then a second method based on laser stimulation is presented, improv- ing the “traditional” attacks by injecting a photocurrent, which results in a punctual increase of the power consumption of a circuit. These tech- niques are demonstrated on an FPGA device

Effect of temperature on superconducting nanowire single-photon detector noise

Today Superconducting Nanowire Single-Photon Detectors (SNSPDs) are commonly used in different photon-starved applications, including testing and diagnostics of VLSI circuits. Detecting very faint signals in the near-infrared wavelength range requires not only good detection efficiency, but also very low Dark Count Rate (DCR) and jitter. For example, low noise is crucial to enable ultra-low voltage optical testing of integrated circuits. The effect of detector temperature and background thermal radiation on the noise of superconducting single-photon detectors made of NbN meanders is studied in this paper. It is shown that two different regimes can be identified in the DCR vs. bias current characteristics. At high bias, the dark count rate is dominated by the intrinsic noise of the detector, while at low bias current it is dominated by the detection of stray photons that get onto the SNSPD. Changing the detector temperature changes its switching current and only affects the high bias branch of the characteristics: a reduction of the DCR can be achieved by lowering the SNSPD base temperature. On the other hand, changing the temperature of the single-photon light source (e.g. the VLSI circuit under test) only affects the low bias regime: a lower target temperature leads to a smaller DCR. © (2015) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.United States. Air Force Research Laboratory. Intelligence Advanced Research Projects Activity (IARPA ) (contract number FA8650-11-C_7105

Hardware Trojan Detection Using Controlled Circuit Aging

This paper reports a novel approach that uses transistor aging in an integrated circuit (IC) to detect hardware Trojans. When a transistor is aged, it results in delays along several paths of the IC. This increase in delay results in timing violations that reveal as timing errors at the output of the IC during its operation. We present experiments using aging-aware standard cell libraries to illustrate the usefulness of the technique in detecting hardware Trojans. Combining IC aging with over-clocking produces a pattern of bit errors at the IC output by the induced timing violations. We use machine learning to learn the bit error distribution at the output of a clean IC. We differentiate the divergence in the pattern of bit errors because of a Trojan in the IC from this baseline distribution. We simulate the golden IC and show robustness to IC-to-IC manufacturing variations. The approach is effective and can detect a Trojan even if we place it far off the critical paths. Results on benchmarks from the Trust-hub show a detection accuracy of $\geq$99%.Comment: 21 pages, 34 figure

Nouvelles méthodes d'imagerie haute résolution pour l'analyse des composants nanoélectroniques

-Utilisation de l interaction non-linéaire entre des impulsions laser (proche infrarouge) ultracourtes et le silicium, en mode d absorption multiphotonique ou de génération d harmoniques optiques, pour la stimulation et le test photo-électrique. - Développement des méthodes d imagerie statique et dynamique pour l analyse de défaillance en appliquant les techniques d optique femtoseconde sur circuits intégrés. - Modélisation de l interaction laser-silicium avec la méthode FDTD (Rsoft).Using the nonlinear interaction between ultra-short laser pulses ( ~ 0.8 m to1.3 m) and silicon, with multi-photon absorption or optical harmonic generation, to achieve photoelectric stimulation and testing. Development of imaging methods for static and dynamic failure analysis techniques using femtosecond laser (TOBIC, 2pLADA) on integrated circuits.BORDEAUX1-Bib.electronique (335229901) / SudocSudocFranceF