Novel resource reservation schemes for optical burst switching

We propose to improve the throughput performance of optical burst switching by using regional controller nodes and window-based reservation. Both methods increase the information available to the intermediate nodes during scheduling decisions. Simulations show that the proposed reservation schemes provide significant improvement in the throughput performance compared with the original optical burst switching when the network is heavily loaded. © 2005 IEEE.published_or_final_versio

Destination directed packet switch architecture for a 30/20 GHz FDMA/TDM geostationary communication satellite network

Emphasis is on a destination directed packet switching architecture for a 30/20 GHz frequency division multiplex access/time division multiplex (FDMA/TDM) geostationary satellite communication network. Critical subsystems and problem areas are identified and addressed. Efforts have concentrated heavily on the space segment; however, the ground segment was considered concurrently to ensure cost efficiency and realistic operational constraints

Destination-directed, packet-switching architecture for 30/20-GHz FDMA/TDM geostationary communications satellite network

A destination-directed packet switching architecture for a 30/20-GHz frequency division multiple access/time division multiplexed (FDMA/TDM) geostationary satellite communications network is discussed. Critical subsystems and problem areas are identified and addressed. Efforts have concentrated heavily on the space segment; however, the ground segment has been considered concurrently to ensure cost efficiency and realistic operational constraints

Control Plane Hardware Design for Optical Packet Switched Data Centre Networks

Optical packet switching for intra-data centre networks is key to addressing traffic requirements. Photonic integration and wavelength division multiplexing (WDM) can overcome bandwidth limits in switching systems. A promising technology to build a nanosecond-reconfigurable photonic-integrated switch, compatible with WDM, is the semiconductor optical amplifier (SOA). SOAs are typically used as gating elements in a broadcast-and-select (B\&S) configuration, to build an optical crossbar switch. For larger-size switching, a three-stage Clos network, based on crossbar nodes, is a viable architecture. However, the design of the switch control plane, is one of the barriers to packet switching; it should run on packet timescales, which becomes increasingly challenging as line rates get higher. The scheduler, used for the allocation of switch paths, limits control clock speed. To this end, the research contribution was the design of highly parallel hardware schedulers for crossbar and Clos network switches. On a field-programmable gate array (FPGA), the minimum scheduler clock period achieved was 5.0~ns and 5.4~ns, for a 32-port crossbar and Clos switch, respectively. By using parallel path allocation modules, one per Clos node, a minimum clock period of 7.0~ns was achieved, for a 256-port switch. For scheduler application-specific integrated circuit (ASIC) synthesis, this reduces to 2.0~ns; a record result enabling scalable packet switching. Furthermore, the control plane was demonstrated experimentally. Moreover, a cycle-accurate network emulator was developed to evaluate switch performance. Results showed a switch saturation throughput at a traffic load 60\% of capacity, with sub-microsecond packet latency, for a 256-port Clos switch, outperforming state-of-the-art optical packet switches

Design and evaluation of high-performance packet switching schemes

The design of high-performance packet switches is essential to efficiently handle the exponential growth of data traffic in the next generation Internet. Shared-memory-based packet switches are known to provide the best possible delay-throughput performance and the lowest packet-loss rate compared with packet switches using other buffering strategies. However, scalability of shared-memory-based switching systems has been restricted by high memory bandwidth requirements, segregation of memory space and centralized control of switching functions that causes the switch performance to degrade as a shared-memory switch is grown in size. The new class of sliding-window based packet switches are known to overcome these problems associated with shared-memory switches. This thesis presents different schemes proposed earlier by Dr. Kumar for use in the sliding-window switch to allocate self-routing parameters. Comparative performance of these schemes have been evaluated in this thesis. The results show the scalability of the switch that can be achieved with different parameter assignment schemes. It is shown that not all assignment schemes have same performance. With appropriate assignment scheme, it is possible to achieve very high throughput-performance and switch size for sliding-window switches

On-board B-ISDN fast packet switching architectures. Phase 2: Development. Proof-of-concept architecture definition report

For the next-generation packet switched communications satellite system with onboard processing and spot-beam operation, a reliable onboard fast packet switch is essential to route packets from different uplink beams to different downlink beams. The rapid emergence of point-to-point services such as video distribution, and the large demand for video conference, distributed data processing, and network management makes the multicast function essential to a fast packet switch (FPS). The satellite's inherent broadcast features gives the satellite network an advantage over the terrestrial network in providing multicast services. This report evaluates alternate multicast FPS architectures for onboard baseband switching applications and selects a candidate for subsequent breadboard development. Architecture evaluation and selection will be based on the study performed in phase 1, 'Onboard B-ISDN Fast Packet Switching Architectures', and other switch architectures which have become commercially available as large scale integration (LSI) devices

An assembly and offset assignment scheme for self-similar traffic in optical burst switching

Includes bibliographical references.Optical Burst Switching (OBS) is a viable technology for the next generation core network. We propose an FEC-assembly scheme that efficiently assembles self-similar traffic and a Pareto-offset assignment rather than a constant offset assignment. Two buffers, a packet buffer and a burst buffer, are implemented at the Label Edge Router (LER), buffering traffic in the electronic domain. The assembler, between the packet and burst buffers, is served by the packet queue while the assembler serves the burst queue. We outline advantages of why burst assembly cannot be implemented independent of offset assignment. The two schemes must be implemented in a complementary way if QoS is to be realized in an OBS network. We show that there is a direct relation between OBS network performance with burst assembly and offset assignment. We present simulation results of the assembly and offset assignment proposals using the ns2 network simulator. Our results show that the combination of the proposed FEC-Based assembly scheme with the proposed Pareto-offset assignment scheme give better network performance in terms of burst drop, resource contention and delay. Key to any traffic shaping is the nature traffic being shaped. This work also compares performance of both traditional exponential traffic with realistic Self-Similar traffic of Internet traffic on the proposed assembly and offset assignment schemes. In our simulations, we assume that all Label Switch Routers (LSR) have wavelength converters and are without optical buffers. We use Latest Available Unused Channel with Void Filling (LAUC-VF) scheduling scheme and use Just Enough Time (JET) reservation scheme