A PLL based built-in self-test for MEMS sensors

A new readout circuit for capacitive Micro-Electrical-Mechanical System (MEMS) devices has been proposed, developed and simulated in this thesis. The readout circuit utilizes a Phase Locked Loop (PLL) to convert variations of MEM capacitance to time domain signals. The proposed circuit demonstrates a robust performance against process, power supply and temperature variations due to inherent feedback of PLL systems. Post layout simulation results in Cadence environment using TSMC CMOS 65nm technology indicate that the implemented readout circuit can successfully measure and detect minor variations of MEMS capacitance from its nominal value

Built-In Self-Test Solution for CMOS MEMS Sensors

This thesis presents a new readout circuit with integrated Built-in Self-Test (BIST) structure for capacitive Micro-Electro-Mechanical Systems (MEMS). In the proposed solution instead of commonly used voltage control signals to test the device, charge control stimuli are employed to cover a wider range of structural defects. The proposed test solution eliminates the risk of MEMS structural collapse in the test phase. Measurement results using a prototype fabricated in TSMC 65nm CMOS technology indicate that the proposed BIST scheme can successfully detect minor structural defects altering MEMS nominal capacitance