Analysis of interconnection networks in heterogeneous multi-cluster systems

The study of interconnection networks is important because the overall performance of a distributed system is often critically hinged on the effectiveness of its interconnection network. In the mean time, the heterogeneity is one of the most important factors of such systems. This paper addresses the problem of interconnection networks performance modeling of large-scale distributed systems with emphases on heterogeneous multi-cluster computing systems. So, we present an analytical model to predict message latency in multi-cluster systems in the presence of cluster size heterogeneity. The model is validated through comprehensive simulation, which demonstrates that the proposed model exhibits a good degree of accuracy for various system organizations and under different working conditions.<br /

Analytical interconnection networks model for multi-cluster computing systems

This paper addresses the problem of interconnection networks performance modeling of large-scale distributed systems with emphases on multi-cluster computing systems. The study of interconnection networks is important because the overall performance of a distributed system is often critically hinged on the effectiveness of its interconnection network. We present an analytical model that considers stochastic quantities as well as processor heterogeneity of the target system. The model is validated through comprehensive simulation, which demonstrates that the proposed model exhibits a good degree of accuracy for various system sizes and under different operating conditions.<br /

Multi-cluster computing interconnection network performance modeling and analysis

The overall performance of a distributed system is often depends on the effectiveness of its interconnection network. Thus, the study of the communication networks for distributed systems is very important, which is the focus of this paper. In particular, we address the problem of fat-tree based interconnection networks performance modeling for multi-user heterogeneous multi-cluster computing systems. To this end, we present an analytical model and validate the model through comprehensive simulation. The results of the simulation demonstrated that the proposed model exhibits a good degree of accuracy for various system organizations and under different working conditions

An analytical model of multi-core multi-cluster architecture (MCMCA)

Multi-core clusters have emerged as an important contribution in computing technology for provisioning additional processing power in high performance computing and communications. Multi-core architectures are proposed for their capability to provide higher performance without increasing heat and power usage, which is the main concern in a single-core processor. This paper introduces analytical models of a new architecture for large-scale multi-core clusters to improve the communication performance within the interconnection network. The new architecture will be based on a multi - cluster architecture containing clusters of multi-core processor

Analysis of multi-cluster computing systems with processor heterogeneity

This paper addresses the problem of performance modeling of heterogeneous multi-cluster computing systems. We present an analytical model that can be employed to explore the effectiveness of different design approaches so that one can have an intelligent choice during design and evaluation of a cost effective large-scale heterogeneous distributed computing system. The proposed model considers stochastic quantities as well as processor heterogeneity of the target system. The analysis is based on a parametric fat-tree network, the m-port n-tree, and a deterministic routing algorithm. The correctness of the proposed model is validated through comprehensive simulation of different types of clusters.<br /

Quarc: an architecture for efficient on-chip communication

The exponential downscaling of the feature size has enforced a paradigm shift from computation-based design to communication-based design in system on chip development. Buses, the traditional communication architecture in systems on chip, are incapable of addressing the increasing bandwidth requirements of future large systems. Networks on chip have emerged as an interconnection architecture offering unique solutions to the technological and design issues related to communication in future systems on chip. The transition from buses as a shared medium to networks on chip as a segmented medium has given rise to new challenges in system on chip realm. By leveraging the shared nature of the communication medium, buses have been highly efficient in delivering multicast communication. The segmented nature of networks, however, inhibits the multicast messages to be delivered as efficiently by networks on chip. Relying on extensive research on multicast communication in parallel computers, several network on chip architectures have offered mechanisms to perform the operation, while conforming to resource constraints of the network on chip paradigm. Multicast communication in majority of these networks on chip is implemented by establishing a connection between source and all multicast destinations before the message transmission commences. Establishing the connections incurs an overhead and, therefore, is not desirable; in particular in latency sensitive services such as cache coherence. To address high performance multicast communication, this research presents Quarc, a novel network on chip architecture. The Quarc architecture targets an area-efficient, low power, high performance implementation. The thesis covers a detailed representation of the building blocks of the architecture, including topology, router and network interface. The cost and performance comparison of the Quarc architecture against other network on chip architectures reveals that the Quarc architecture is a highly efficient architecture. Moreover, the thesis introduces novel performance models of complex traffic patterns, including multicast and quality of service-aware communication

Analytical modeling of communication latency in multi-cluster systems

This paper addresses the problem of performance modeling of large-scale distributed systems with emphasis on communication networks in heterogeneous multi-cluster systems. The study of interconnection networks is important because the overall performance of a distributed system is often critically hinged on the effectiveness of this part. We present an analytical model to predict message latency in multi-cluster systems in the presence of processor heterogeneity. The model is validated through comprehensive simulation, which demonstrates that the proposed model exhibits a good degree of accuracy for various system sizes and under different operating conditions.<br /

An Efficient Medium Access Control Strategy for High Speed WDM Multiaccess Networks

A medium access control (MAC) strategy that accounts for the limited tunability of present-day lasers and filters and yet supports a large total number of wavelengths in the network is proposed. Full interconnectivity, contention-free access and a high value of concurrency are achieved by dividing the network into disjunct subnetworks on a wavelength basis and by reconfiguring these subnetworks on a time basis. Each subnetwork allows for simplified access to be implemented with fast tunable transceivers each assessing only a moderate number of wavelengths. A performance analysis shows that this concept is most efficient when applied to a high-level broadband interconnection metropolitan area network (MAN

Communication network analysis of the enterprise grid systems

This paper addresses the problem of performance analysis based on communication modelling of largescale heterogeneous distributed systems with emphases on enterprise grid computing systems. The study of communication layers is important because the overall performance of a distributed system is often critically hinged on the effectiveness of this part. This model considers processor as well as network heterogeneity of target system. The model is validated through comprehensive simulation, which demonstrates that the proposed model exhibits a good degree of accuracy for various system sizes and under different working conditions. The proposed model is then used to investigate the performance analysis of typical systems.<br /

On the design of a high-performance adaptive router for CC-NUMA multiprocessors

Copyright © 2003 IEEEThis work presents the design and evaluation of an adaptive packet router aimed at supporting CC-NUMA traffic. We exploit a simple and efficient packet injection mechanism to avoid deadlock, which leads to a fully adaptive routing by employing only three virtual channels. In addition, we selectively use output buffers for implementing the most utilized virtual paths in order to reduce head-of-line blocking. The careful implementation of these features has resulted in a good trade off between network performance and hardware cost. The outcome of this research is a High-Performance Adaptive Router (HPAR), which adequately balances the needs of parallel applications: minimal network latency at low loads and high throughput at heavy loads. The paper includes an evaluation process in which HPAR is compared with other adaptive routers using FIFO input buffering, with or without additional virtual channels to reduce head-of-line blocking. This evaluation contemplates both the VLSI costs of each router and their performance under synthetic and real application workloads. To make the comparison fair, all the routers use the same efficient deadlock avoidance mechanism. In all the experiments, HPAR exhibited the best response among all the routers tested. The throughput gains ranged from 10 percent to 40 percent in respect to its most direct rival, which employs more hardware resources. Other results shown that HPAR achieves up to 83 percent of its theoretical maximum throughput under random traffic and up to 70 percent when running real applications. Moreover, the observed packet latencies were comparable to those exhibited by simpler routers. Therefore, HPAR can be considered as a suitable candidate to implement packet interchange in next generations of CC-NUMA multiprocessors.Valentín Puente, José-Ángel Gregorio, Ramón Beivide, and Cruz Iz