Precision packet-based frequency transfer based on oversampling

Frequency synchronization of a distributed measurement system requires the transfer of an accurate frequency reference to all nodes. The use of a general-purpose packet-based network for this aim is analyzed in this paper, where oversampling is considered as a means to counter the effects of packet delay variation on time accuracy. A comprehensive analysis that includes the stability of the local clock is presented and shows that frequency transfer through a packet network of this kind is feasible, with an accuracy level that can be of interest to a number of distributed measurement applications

An Enhanced IEEE1588 Clock Synchronization for Link Delays Based on a System-on-Chip Platform

The clock synchronization is considered as a key technology in the time-sensitive networking (TSN) of 5G fronthaul. This paper proposes a clock synchronization enhancement method to optimize the link delays, in order to improve synchronization accuracy. First, all the synchronization dates are filtered twice to get the good calculation results in the processor, and then FPGA adjust the timer on the slave side to complete clock synchronization. This method is implemented by Xilinx Zynq UltraScale+ MPSoC (multiprocessor system-on-chip), using FPGA+ARM software and hardware co-design platform. The master and slave output Pulse Per-Second (PPS) signals. The synchronization accuracy was evaluated by measuring the time offset between PPS signals. Contraposing the TSN, this paper compares the performance of the proposed scheme with some previous methods to show the efficacy of the proposed work. The results show that the slave clock of proposed method is synchronized with the master clock, leading to better robustness and significant improvement in accuracy, with time offset within the range of 40 nanoseconds. This method can be applied to the time synchronization of the 5G open fronthaul network and meets some special service needs in 5G communication

An Enhanced IEEE1588 Clock Synchronization for Link Delays Based on a System-on-Chip Platform

The clock synchronization is considered as a key technology in the time-sensitive networking (TSN) of 5G fronthaul. This paper proposes a clock synchronization enhancement method to optimize the link delays, in order to improve synchronization accuracy. First, all the synchronization dates are filtered twice to get the good calculation results in the processor, and then FPGA adjust the timer on the slave side to complete clock synchronization. This method is implemented by Xilinx Zynq UltraScale+ MPSoC (multiprocessor system-on-chip), using FPGA+ARM software and hardware co-design platform. The master and slave output Pulse Per-Second (PPS) signals. The synchronization accuracy was evaluated by measuring the time offset between PPS signals. Contraposing the TSN, this paper compares the performance of the proposed scheme with some previous methods to show the efficacy of the proposed work. The results show that the slave clock of proposed method is synchronized with the master clock, leading to better robustness and significant improvement in accuracy, with time offset within the range of 40 nanoseconds. This method can be applied to the time synchronization of the 5G open fronthaul network and meets some special service needs in 5G communication

Research on Mobile Network High-precision Absolute Time Synchronization based on TAP

With the development of mobile communication and industrial internet technologies, the demand for robust absolute time synchronization based on network for diverse scenarios is significantly growing. TAP is a novel network timing method that aims to achieve sub-microsecond synchronization over air interface. This paper investigates the improvement and end-to-end realization of TAP. This paper first analyzes the effectiveness and deficiencies of TAP by establishing an equivalent clock model which evaluates TAP from timing error composition and allan variance. Second, this paper proposes a detailed base station and terminal design and the corresponding improvement of TAP. Both hardware compensation and protocol software design are taken into account so as to minimize timing error and system cost while maximizing compatibility with 3GPP. Finally, this paper presents a TAP end-to-end 5G prototype system developed based on software defined radio base station and COTS baseband module. The field test results show that the proposed scheme effectively solves the problems of TAP in application and robustly achieves 200ns level timing accuracy in various situations. The average accuracy with long observations can reach 1 nanosecond. It is 2$\sim$3 orders of magnitude better than common network timing methods, including NTP, PTP and the original TAP

Proportional-Integral Synchronisation for Non-identical Wireless Packet-Coupled Oscillators with Delays

Precise timing among wireless sensor nodes is a key enabling technology for time-sensitive industrial Wireless Sensor Networks (WSNs). However, the accuracy of timing is degraded by manufacturing tolerance, ageing of crystal oscillators, and communication delays. This paper develops a framework of Packet-Coupled Oscillator (PkCOs) to characterise the dynamics of communication and time synchronisation of clocks in WSNs. A non-identical clock is derived to describe the embedded clock's behaviour accurately. The Proportional-Integral (PI) packet coupling scheme is proposed for synchronising networked embedded clocks, meanwhile, scheduling wireless Sync packets to different slots for transmission. It also possesses the feature of automatically eliminating the effects of unknown processing delay, which further improves synchronisation performance. The rigorous theoretical analysis of PI-based PkCOs is presented via studying a closed-loop time synchronisation system. The performance of PI-based PkCOs is evaluated on a hardware testbed of IEEE 802.15.4 WSN. The experimental results show that the precision of the proportional-integral PkCOs protocol is as high as 60us (i.e., 2 ticks) for 32.768kHz crystal oscillator-based clocks