Area-Delay-Efficeint FPGA Design of 32-bit Euclid's GCD based on Sum of Absolute Difference

Euclids algorithm is widely used in calculating of GCD (Greatest Common Divisor) of two positive numbers. There are various fields where this division is used such as channel coding, cryptography, and error correction codes. This makes the GCD a fundamental algorithm in number theory, so a number of methods have been discovered to efficiently compute it. The main contribution of this paper is to investigate a method that computes the GCD of two 32-bit numbers based on Euclidean algorithm which targets six different Xilinx chips. The complexity of this method that we call Optimized_GCDSAD is achieved by utilizing Sum of Absolute Difference (SAD) block which is based on a fast carry-out generation function. The efficiency of the proposed architecture is evaluated based on criteria such as time (latency), area delay product (ADP) and space (slice number) complexity. The VHDL codes of these architectures have been implemented and synthesized through ISE 14.7. A detailed comparative analysis indicates that the proposed Optimized_GCDSAD method based on SAD block outperforms previously known results

Authentication system for e-certificate by using RSA’s digital signature

Online learning and teaching become the popular channel for all participants, because they can access the courses everywhere with the high-speed internet. E-certificate is being prepared for everyone who has participated or passed the requirements of the courses. Because of many benefits frome-certificate, it may become the demand for intruders to counterfeit the certificate. In this paper, Rivest-Shamir-Adleman (RSA)’s digital signature is chosen to signe-certificate in order to avoid being counterfeited by intruders. There are two applications to managee-certificate. The first application is the signing application to sign the sub image including only participant’s name in e-certificate. In general, the file of digital signature is divided frome-certificate. That means, both of them must be selected to compare each other in checking application. In fact, the solution will be approved when each pixel of participant’s name is equal to each part from the decrypted message at the same position. In experimental session, 40 e-certificatesare chosen for the implementation. The results reveal that the accuracy is 100% and both of signing and checking processes are completed rapidly fast, especially when signing application is applied with Chinese remainder theorem (CRT) or the special technique of CRT. Therefore, the proposed method is one of the best solutions to protect e-certificate from the forgery by intruders

Improving the initial values of VFactor suitable for balanced modulus

The aim of this study is to estimate the new initial values of VFactor. In general, this algorithm is one of the members in a group of special proposed integer factorization algorithm. It has very high performance whenever the result of the difference between two prime factors of the modulus is a little, it is also called as balanced modulus. In fact, if this situation is occurred, RSA which is a type of public key cryptosystem will be broken easily. In addition, the main process of VFactor is to increase and decrease two odd integers in order to compute the multiplication until the targets are found. However, the initial values are far from the targets especially that the large value of the difference between two prime factors that is not suitable for VFactor. Therefore, the new initial values which are closer to the targets than the traditional values are proposed to decrease loops of the computation. In experimental results, it is shown that the loops can be decreased about 26% for the example of 256 bits-length of modulus that is from the small result of the difference between prime factors