Performances Concatenated LDPC based STBC-OFDM System and MRC Receivers

This paper presents the bit error rate performance of the low density parity check (LDPC) with the concatenation of convolutional channel coding based orthogonal frequency-division-multiplexing (OFDM) using space time block coded (STBC). The OFDM wireless communication system incorporates 3/4-rated convolutional encoder under various digital modulations (BPSK, QPSK and QAM) over an additative white gaussian noise (AWGN) and fading (Raleigh and Rician) channels. At the receiving section of the simulated system, Maximum Ratio combining (MRC) channel equalization technique has been implemented to extract transmitted symbols without enhancing noise power

Design and Performance Analysis for LDPC Coded Modulation in Multiuser MIMO Systems

The channel capacity can be greatly increased by using multiple transmit and receive antennas, which is usually called multi-input multi-output (MIMO) systems. Iterative processing has achieved near-capacity on a single-antenna Gaussian or Rayleigh fading channel. How to use the iterative technique to exploit the capacity potential in single-user and/or multiuser MIMO systems is of great interest. We propose a low-density parity-check (LDPC) coded modulation scheme in multiuser MIMO systems. The receiver can be regarded as a serially concatenated iterative detection and decoding scheme, where the LDPC decoder performs the role of outer decoder and the multiuser demapper does that of the inner decoder. For the proposed scheme, appropriate selection of a bit-to-symbol mapping is crucial to achieve a good performance, so we investigate and find the best mapping under various cases.Analytical bound serves as a useful tool to assess system performance. The search for powerful codes has motivated the introduction of efficient bounding techniques tailored to some ensembles of codes. We then investigate combinatorial union bounding techniques for fast fading multiuser MIMO systems. The union upper bound on maximum likelihood (ML) decoding error probability provides a prediction for the system performance, with which the simulated system performance can be compared. Closed-form expression for the union bound is obtained, which can be evaluated efficiently by using a polynomial expansion. In addition, the constrained channel capacity and the threshold obtained from extrinsic information transfer (EXIT) chart can also serve as performance measures. Based on the analysis for fast fading case, we generalize the union upper bound to the block fading case

FPGA Implementation of Low Density Party Check Codes Decoder

Reliable communication over the noisy channel has become one of the major concerns in the field of digital wireless communications. The low density parity check codes (LDPC) has gained lot of attention recently because of their excellent error-correcting capacity. It was first proposed by Robert G. Gallager in 1960. LDPC codes belong to the class of linear block codes. Near capacity performance is achievable on a large collection of data transmission and storage.In my thesis I have focused on hardware implementation of (3, 6) - regular LDPC codes. A fully parallel decoder will require too high complexity of hardware realization. Partly parallel decoder has the advantage of effective compromise between decoding throughput and high hardware complexity. The decoding of the codeword follows the belief propagation alias probability propagation algorithm in log domain. A 9216 bit, (3, 6) regular LDPC code with code rate ½ was implemented on FPGA targeting Xilinx Virtex 4 XC4VLX80 device with package FF1148. This decoder achieves a maximum throughput of 82 Mbps. The entire model was designed in VHDL in the Xilinx ISE 9.2 environment