Design for manufacturability : re-design of pencil sharpener for the ease of assembly

A Design For Manufacturability (DFM) approach is used to analyze the existing design of a pencil sharpener, and to reduce and re-design the parts of pencil sharpener for the ease of assembly. The procedure for the selection of a suitable and economical assembly method is based on the Boothroyd and Dewhurst methods. Analysis of the initial design for manual assembly and re-design for automatic as well as manual assembly is presented. An algorithmic approach for simplified generation of all mechanical assembly sequences and selection of the assembly sequences is presented using De Fazio and Whitney approach

PROBE3.0: A Systematic Framework for Design-Technology Pathfinding with Improved Design Enablement

We propose a systematic framework to conduct design-technology pathfinding for PPAC in advanced nodes. Our goal is to provide configurable, scalable generation of process design kit (PDK) and standard-cell library, spanning key scaling boosters (backside PDN and buried power rail), to explore PPAC across given technology and design parameters. We build on PROBE2.0, which addressed only area and cost (AC), to include power and performance (PP) evaluations through automated generation of full design enablements. We also improve the use of artificial designs in the PPAC assessment of technology and design configurations. We generate more realistic artificial designs by applying a machine learning-based parameter tuning flow. We further employ clustering-based cell width-regularized placements at the core of routability assessment, enabling more realistic placement utilization and improved experimental efficiency. We demonstrate PPAC evaluation across scaling boosters and artificial designs in a predictive technology node.Comment: 14 pages, 17 figures, submitted to IEEE Trans. on CA

The Design of Crowd-Funded Products

Crowdfunding is an emerging phenomenon where entrepreneurs publicize their product concepts to raise development funding and collect design feedback directly from potential supporters. Many innovative products have raised a significant amount of crowdfunding. This paper analyzes the crowd-funded products to develop design guidelines for crowdfunding success. A database of 127 samples is collected in two different product categories from two different crowdfunding websites. They are evaluated using a design project assessment scorecard, the Real-Win-Worth framework, which focuses on the state of maturity on various customer, technical and supply chain dimensions. Our analysis identified key RWW factors that characterize successful design for crowd-funded products. For example, success at crowdfunding is attained through clear explanation of how the design operates technically and meets customer needs. Another recommendation is to not emphasize patent protection, for which crowd-funders are less concerned. Also, evidence of a strong startup financial plan is not necessary for crowdfunding success. These key RWW factors provide guidelines for designers and engineers to improve their design and validate their concepts early to improve their chances for success on crowdfunding platforms.SUTD-MIT International Design Centre (IDC

The Potential of Establishing Technology Computer Aided Design Industry: Africa - Sudan As a Case-Study

Very-Large-Scale-Integration (VLSI) Integrated-Circuit (IC) designs have steadily grown in their capacity and complexity through the years. The need for technology simulations using technology computer-aided-design (TCAD) tools have become an essential part of design success. The TCAD simulations facilitate process optimization, highlight device performance tradeoffs, enable worst case analysis, and reveal device defects and weakness. Microelectronics higher education in African universities focuses mainly on the chip/circuit design instruction. Virtually little or no emphasis is applied to grow students TCAD simulation skills. This paper discusses the potential of African educational institutes of becoming the supplier of qualified TCAD simulation engineers for future African IC industry and/or worldwide VLSI job market. The African universities are encouraged to emphasize on establishing frameworks that would include TCAD simulation research and development into their curriculums and motivate students to venture the VLSI design and automation fields. This would enable African graduates to exploit the microelectronics job market worldwide and establish TCAD industries within Africa to industrialize African job market

Towards Structural Testing of Superconductor Electronics

Many of the semiconductor technologies are already\ud facing limitations while new-generation data and\ud telecommunication systems are implemented. Although in\ud its infancy, superconductor electronics (SCE) is capable of\ud handling some of these high-end tasks. We have started a\ud defect-oriented test methodology for SCE, so that reliable\ud systems can be implemented in this technology. In this\ud paper, the details of the study on the Rapid Single-Flux\ud Quantum (RSFQ) process are presented. We present\ud common defects in the SCE processes and corresponding\ud test methodologies to detect them. The (measurement)\ud results prove that we are able to detect possible random\ud defects for statistical purposes in yield analysis. This\ud paper also presents possible test methodologies for RSFQ\ud circuits based on defect oriented testing (DOT)

Layout-level Circuit Sizing and Design-for-manufacturability Methods for Embedded RF Passive Circuits

The emergence of multi-band communications standards, and the fast pace of the consumer electronics markets for wireless/cellular applications emphasize the need for fast design closure. In addition, there is a need for electronic product designers to collaborate with manufacturers, gain essential knowledge regarding the manufacturing facilities and the processes, and apply this knowledge during the design process. In this dissertation, efficient layout-level circuit sizing techniques, and methodologies for design-for-manufacturability have been investigated. For cost-effective fabrication of RF modules on emerging technologies, there is a clear need for design cycle time reduction of passive and active RF modules. This is important since new technologies lack extensive design libraries and layout-level electromagnetic (EM) optimization of RF circuits become the major bottleneck for reduced design time. In addition, the design of multi-band RF circuits requires precise control of design specifications that are partially satisfied due to manufacturing variations, resulting in yield loss. In this work, a broadband modeling and a layout-level sizing technique for embedded inductors/capacitors in multilayer substrate has been presented. The methodology employs artificial neural networks to develop a neuro-model for the embedded passives. Secondly, a layout-level sizing technique for RF passive circuits with quasi-lumped embedded inductors and capacitors has been demonstrated. The sizing technique is based on the circuit augmentation technique and a linear optimization framework. In addition, this dissertation presents a layout-level, multi-domain DFM methodology and yield optimization technique for RF circuits for SOP-based wireless applications. The proposed statistical analysis framework is based on layout segmentation, lumped element modeling, sensitivity analysis, and extraction of probability density functions using convolution methods. The statistical analysis takes into account the effect of thermo-mechanical stress and process variations that are incurred in batch fabrication. Yield enhancement and optimization methods based on joint probability functions and constraint-based convex programming has also been presented. The results in this work have been demonstrated to show good correlation with measurement data.Ph.D.Committee Chair: Swaminathan, Madhavan; Committee Member: Fathianathan, Mervyn; Committee Member: Lim, Sung Kyu; Committee Member: Peterson, Andrew; Committee Member: Tentzeris, Mano

Layout regularity metric as a fast indicator of process variations

Integrated circuits design faces increasing challenge as we scale down due to the increase of the effect of sensitivity to process variations. Systematic variations induced by different steps in the lithography process affect both parametric and functional yields of the designs. These variations are known, themselves, to be affected by layout topologies. Design for Manufacturability (DFM) aims at defining techniques that mitigate variations and improve yield. Layout regularity is one of the trending techniques suggested by DFM to mitigate process variations effect. There are several solutions to create regular designs, like restricted design rules and regular fabrics. These regular solutions raised the need for a regularity metric. Metrics in literature are insufficient for different reasons; either because they are qualitative or computationally intensive. Furthermore, there is no study relating either lithography or electrical variations to layout regularity. In this work, layout regularity is studied in details and a new geometrical-based layout regularity metric is derived. This metric is verified against lithographic simulations and shows good correlation. Calculation of the metric takes only few minutes on 1mm x 1mm design, which is considered fast compared to the time taken by simulations. This makes it a good candidate for pre-processing the layout data and selecting certain areas of interest for lithographic simulations for faster throughput. The layout regularity metric is also compared against a model that measures electrical variations due to systematic lithographic variations. The validity of using the regularity metric to flag circuits that have high variability using the developed electrical variations model is shown. The regularity metric results compared to the electrical variability model results show matching percentage that can reach 80%, which means that this metric can be used as a fast indicator of designs more susceptible to lithography and hence electrical variations