Deadline-ordered parallel iterative matching with QoS guarantee.

by Lui Hung Ngai.Thesis (M.Phil.)--Chinese University of Hong Kong, 2000.Includes bibliographical references (leaves 56-[59]).Abstracts in English and Chinese.Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Thesis Overview --- p.3Chapter 2 --- Background & Related work --- p.4Chapter 2.1 --- Scheduling problem in ATM switch --- p.4Chapter 2.2 --- Traffic Scheduling in output-buffered switch --- p.5Chapter 2.3 --- Traffic Scheduling in Input buffered Switch --- p.16Chapter 3 --- Deadline-ordered Parallel Iterative Matching (DLPIM) --- p.22Chapter 3.1 --- Introduction --- p.22Chapter 3.2 --- Switch model --- p.23Chapter 3.3 --- Deadline-ordered Parallel Iterative Matching (DLPIM) --- p.24Chapter 3.3.1 --- Motivation --- p.24Chapter 3.3.2 --- Algorithm --- p.26Chapter 3.3.3 --- An example of DLPIM --- p.28Chapter 3.4 --- Simulation --- p.30Chapter 4 --- DLPIM with static scheduling algorithm --- p.41Chapter 4.1 --- Introduction --- p.41Chapter 4.2 --- Static scheduling algorithm --- p.42Chapter 4.3 --- DLPIM with static scheduling algorithm --- p.48Chapter 4.4 --- An example of DLPIM with static scheduling algorithm --- p.50Chapter 5 --- Conclusion --- p.54Bibliography --- p.5

Multicast cross-path ATM switches: principles, designs and performance evaluations.

by Lin Hon Man.Thesis (M.Phil.)--Chinese University of Hong Kong, 1998.Includes bibliographical references (leaves 59-[63]).Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Organization of Thesis --- p.3Chapter 2 --- Principles of Multicast Cross-Path Switches --- p.4Chapter 2.1 --- Introduction --- p.4Chapter 2.2 --- Unicast Cross-Path switch --- p.5Chapter 2.2.1 --- Routing properties in Clos networks --- p.5Chapter 2.2.2 --- Quasi-static routing procedures --- p.5Chapter 2.2.3 --- Capacity and Route Assignment --- p.7Chapter 2.3 --- Multicast Cross-Path Switch --- p.8Chapter 2.3.1 --- Scheme 1 - Cell replication performed at both input and output stages --- p.10Chapter 2.3.2 --- Scheme 2 - Cell replication performed only at the input stage --- p.10Chapter 3 --- Architectures --- p.14Chapter 3.1 --- Introduction --- p.14Chapter 3.2 --- Input Module Design (Scheme 1) --- p.16Chapter 3.2.1 --- Input Header Translator --- p.16Chapter 3.2.2 --- Input Module Controller --- p.17Chapter 3.2.3 --- Input Replication Network (Scheme 1) --- p.19Chapter 3.2.4 --- Routing Network --- p.23Chapter 3.3 --- Central Modules --- p.24Chapter 3.4 --- Output Module Design (Scheme 1) --- p.24Chapter 3.5 --- Input Module Design (Scheme 2) --- p.25Chapter 3.5.1 --- Input Header Translator (Scheme 2) --- p.26Chapter 3.5.2 --- Input Module Controller (Scheme 2) --- p.27Chapter 3.5.3 --- Input Replication Network (Scheme 2) --- p.28Chapter 3.6 --- Output Module Design (Scheme 2) --- p.29Chapter 4 --- Performance Evaluations --- p.31Chapter 4.1 --- Introduction --- p.31Chapter 4.2 --- Traffic characteristics --- p.31Chapter 4.2.1 --- Fanout distribution --- p.31Chapter 4.2.2 --- Middle stage traffic load and its calculation --- p.32Chapter 4.3 --- Throughput Performance --- p.34Chapter 4.4 --- Delay Performance --- p.37Chapter 4.4.1 --- Input Stage Delay --- p.38Chapter 4.4.2 --- Output Stage Delay --- p.39Chapter 4.5 --- Cell Loss Performance --- p.43Chapter 4.5.1 --- Cell Loss due to Buffer Overflow --- p.44Chapter 4.5.2 --- Cell Loss Due to Output Contention --- p.45Chapter 4.6 --- Complexities --- p.50Chapter 5 --- Conclusions --- p.57Bibliography --- p.5

Investigation of the tolerance of wavelength-routed optical networks to traffic load variations.

This thesis focuses on the performance of circuit-switched wavelength-routed optical network with unpredictable traffic pattern variations. This characteristic of optical networks is termed traffic forecast tolerance. First, the increasing volume and heterogeneous nature of data and voice traffic is discussed. The challenges in designing robust optical networks to handle unpredictable traffic statistics are described. Other work relating to the same research issues are discussed. A general methodology to quantify the traffic forecast tolerance of optical networks is presented. A traffic model is proposed to simulate dynamic, non-uniform loads, and used to test wavelength-routed optical networks considering numerous network topologies. The number of wavelengths required and the effect of the routing and wavelength allocation algorithm are investigated. A new method of quantifying the network tolerance is proposed, based on the calculation of the increase in the standard deviation of the blocking probabilities with increasing traffic load non-uniformity. The performance of different networks are calculated and compared. The relationship between physical features of the network topology and traffic forecast tolerance is investigated. A large number of randomly connected networks with different sizes were assessed. It is shown that the average lightpath length and the number of wavelengths required for full interconnection of the nodes in static operation both exhibit a strong correlation with the network tolerance, regardless of the degree of load non-uniformity. Finally, the impact of wavelength conversion on network tolerance is investigated. Wavelength conversion significantly increases the robustness of optical networks to unpredictable traffic variations. In particular, two sparse wavelength conversion schemes are compared and discussed: distributed wavelength conversion and localized wavelength conversion. It is found that the distributed wavelength conversion scheme outperforms localized wavelength conversion scheme, both with uniform loading and in terms of the network tolerance. The results described in this thesis can be used for the analysis and design of reliable WDM optical networks that are robust to future traffic demand variations

Reconfiguration issues in a quasi-static packet switch.

by Man Wai-Hung.Thesis (M.Phil.)--Chinese University of Hong Kong, 2003.Includes bibliographical references (leaves 62-66).Abstracts in English and Chinese.Chapter 1 --- Introduction --- p.1Chapter 1.1 --- General Types of Switch Architecture --- p.2Chapter 1.1.1 --- Input-Buffered Switch --- p.2Chapter 1.1.2 --- Output-Buffered Switch --- p.4Chapter 1.1.3 --- Crossbar-Based Switch --- p.4Chapter 1.1.4 --- Shared Buffer Memory Switch --- p.5Chapter 1.2 --- From Clos Network to Cross-path Switch --- p.6Chapter 1.3 --- Motivation and Organization --- p.12Chapter 2 --- Route Reconfiguration in Clos Network --- p.14Chapter 2.1 --- Connection Matrix in Clos Network --- p.15Chapter 2.2 --- Rearranging Central Modules in Clos Network --- p.18Chapter 2.3 --- Changing the Connection Matrix --- p.20Chapter 2.4 --- One Step Route Reconfiguration --- p.21Chapter 2.5 --- Closing Remarks --- p.25Chapter 3. --- Frame-Based Reconfiguration Scheme in Cross-Path Switch --- p.26Chapter 3.1 --- Route Assignment in Cross-Path Switch --- p.27Chapter 3.1.1 --- Requirement Matrix and Capacity Matrix --- p.27Chapter 3.1.2 --- Allocation Vector --- p.29Chapter 3.2 --- Progress Tracing in Cross-Path Switch --- p.30Chapter 3.3 --- Implementing Frame-Based Reconfiguration --- p.32Chapter 3.3.1 --- Recognizing Receiver Virtual Path --- p.33Chapter 3.3.2 --- Finding Donor Virtual Path --- p.34Chapter 3.4 --- Simulation Results --- p.36Chapter 3.4.1 --- Fixed Requirement Matrix --- p.36Chapter 3.4.2 --- Time-Varying Requirement Matrix --- p.38Chapter 3.5 --- Unfavourable Reconfigurations --- p.39Chapter 3.6 --- Closing Remarks --- p.41Chapter 4. --- Performance and Delay Tradeoff in Frame-Based Reconfiguration Scheme --- p.43Chapter 4.1 --- Service Curve and Cross-Path Switch --- p.44Chapter 4.2 --- Service Curve of Cross-Path Switch under Reconfiguration --- p.45Chapter 4.3 --- Impact of Reconfiguration Algorithms to Maximum Delay Increase --- p.48Chapter 4.4 --- Numerical Example --- p.56Chapter 4.5 --- Closing Remarks --- p.57Chapter 5. --- Conclusions and Future Researches --- p.59Chapter 5.1 --- Suggestions for Future Researches --- p.60Bibliography --- p.6

Dynamic bandwidth allocation in ATM networks

Includes bibliographical references.This thesis investigates bandwidth allocation methodologies to transport new emerging bursty traffic types in ATM networks. However, existing ATM traffic management solutions are not readily able to handle the inevitable problem of congestion as result of the bursty traffic from the new emerging services. This research basically addresses bandwidth allocation issues for bursty traffic by proposing and exploring the concept of dynamic bandwidth allocation and comparing it to the traditional static bandwidth allocation schemes

Applications of satellite technology to broadband ISDN networks

Two satellite architectures for delivering broadband integrated services digital network (B-ISDN) service are evaluated. The first is assumed integral to an existing terrestrial network, and provides complementary services such as interconnects to remote nodes as well as high-rate multicast and broadcast service. The interconnects are at a 155 Mbs rate and are shown as being met with a nonregenerative multibeam satellite having 10-1.5 degree spots. The second satellite architecture focuses on providing private B-ISDN networks as well as acting as a gateway to the public network. This is conceived as being provided by a regenerative multibeam satellite with on-board ATM (asynchronous transfer mode) processing payload. With up to 800 Mbs offered, higher satellite EIRP is required. This is accomplished with 12-0.4 degree hopping beams, covering a total of 110 dwell positions. It is estimated the space segment capital cost for architecture one would be about $190M whereas the second architecture would be about$250M. The net user cost is given for a variety of scenarios, but the cost for 155 Mbs services is shown to be about $15-22/minute for 25 percent system utilization

Traffic Control and Distributed Optimization Routing Problems in ATM Networks

Aggressive research as gigabit network has led to dramatic improvements in network transmission speeds. One result of these improvements has been to put pressure on router technology to keep peace. This paper describes a router nearly completed. This is more than fast enough to keep up with the latest transmission technology. This router has a back place speed of 50 gigabit and can forward tens of millions packet.Scheduling algorithm can be implemented on CVAR applications but in this research scheduling is implemented on CBR applications and the performance on WLAN network is enclosed by delivering different traffic load. QOS parameters [5] will be considered as the performance metrics on this study. The comparative study of various algorithms can show the best scheduling algorithm in WLAN with CBR applications.ATM was the focus of action research and significant investment in the early to mid 1990’s. This paper discuss several visions for ATM prevalent at the time and analyses how ATM evolved during this period this paper also consider the amplifications of this history for current connection oriented technologies such as optical transport network and MPLS

Deadline-ordered burst-based parallel scheduling strategy for IP-over-ATM with QoS support.

Siu Chun.Thesis (M.Phil.)--Chinese University of Hong Kong, 2001.Includes bibliographical references (leaves 66-68).Abstracts in English and Chinese.Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Thesis Overview --- p.3Chapter 2 --- Background and Related work --- p.4Chapter 2.1 --- Emergence of IP-over-ATM --- p.4Chapter 2.2 --- ATM architecture --- p.5Chapter 2.3 --- Scheduling issues in output-queued switch --- p.6Chapter 2.4 --- Scheduling issues in input-queued switch --- p.18Chapter 3 --- The Deadline-ordered Burst-based Parallel Scheduling Strategy --- p.23Chapter 3.1 --- Introduction --- p.23Chapter 3.2 --- Switch and queueing model --- p.24Chapter 3.2.1 --- Switch model --- p.24Chapter 3.2.2 --- Queueing model --- p.25Chapter 3.3 --- The DBPS Strategy --- p.26Chapter 3.3.1 --- Motivation --- p.26Chapter 3.3.2 --- Strategy --- p.31Chapter 3.4 --- The Deadline-ordered Burst-based Parallel Iterative Matching --- p.33Chapter 3.4.1 --- Algorithm --- p.34Chapter 3.4.2 --- An example of DBPIM --- p.35Chapter 3.5 --- Simulation results --- p.33Chapter 3.6 --- Discussions --- p.46Chapter 3.7 --- Future work --- p.47Chapter 4 --- The Quasi-static DBPIM Algorithm --- p.50Chapter 4.1 --- Introduction --- p.50Chapter 4.2 --- Quasi-static path scheduling principle --- p.51Chapter 4.3 --- Quasi-static DBPIM algorithm --- p.56Chapter 4.4 --- An example of Quasi-static DBPIM --- p.59Chapter 5 --- Conclusion --- p.63Bibliography --- p.6