Model development via delay extraction for the time-domain simulation of lossy transmission lines.

This thesis presents two new approaches for the broadband, time-domain modeling of lossy transmission lines. Each approach is based on an alternative derivation of delay extraction in order to separate the line's linear phase from its attenuation and dispersion. Augmentation networks represent the derived attenuation networks as rational function approximations. Final network models are implemented in a SPICE circuit simulator for transient analysis. The first approach to extract delay is based on the properties of the eigenvectors of the matrix exponential function in the solution to the telegrapher's equations. The resultant network contains an ideal transmission line cascaded with two asymmetrical delayless attenuation networks. When applied to a single line with constant line parameters, the resultant attenuation networks are inherently non-passive and to which accurate low-order broadband approximations are not possible. The effects of alternative mathematical techniques such as factorization, forcing reciprocity, and eigenvector normalization or scaling, are applied to determine if passive, low-order approximations of the augmentation networks are obtainable. The second approach utilizes a similarity transformation at each transmission line port to obtain commutable matrix exponentials in order to extract delay. The resulting model includes a cascade of one or more delayless networks, an ideal transmission line of unity characteristic impedance, and transformation networks at each port. This approach is applied to single and coupled lines at lengths ranging from 5 cm to 10 m and frequencies up to 5 GHz. The resultant time-domain models are accurate with low-order approximations for lines with constant, non-zero per-unit-length parameters. Lines with zero shunt conductance or frequency-dependent line parameters prove difficult to accurately model at low-orders with this approach

Electrical performance analysis of high-speed interconnects and circuits by numerical modeling methods

Ph.DDOCTOR OF PHILOSOPH

Advanced modelling and design considerations for interconnects in ultra- low power digital system

PhD ThesisAs Very Large Scale Integration (VLSI) is progressing in very Deep submicron (DSM) regime without decreasing chip area, the importance of global interconnects increases but at the cost of performance and power consumption for advanced System-on- Chip (SoC)s. However, the growing complexity of interconnects behaviour presents a challenge for their adequate modelling, whereby conventional circuit theoretic approaches cannot provide sufficient accuracy. During the last decades, fractional differential calculus has been successfully applied to modelling certain classes of dynamical systems while keeping complexity of the models under acceptable bounds. For example, fractional calculus can help capturing inherent physical effects in electrical networks in a compact form, without following conventional assumptions about linearization of non-linear interconnect components. This thesis tackles the problem of interconnect modelling in its generality to simulate a wide range of interconnection configurations, its capacity to emulate irregular circuit elements and its simplicity in the form of responsible approximation. This includes modelling and analysing interconnections considering their irregular components to add more flexibility and freedom for design. The aim is to achieve the simplest adaptable model with the highest possible accuracy. Thus, the proposed model can be used for fast computer simulation of interconnection behaviour. In addition, this thesis proposes a low power circuit for driving a global interconnect at voltages close to the noise level. As a result, the proposed circuit demonstrates a promising solution to address the energy and performance issues related to scaling effects on interconnects along with soft errors that can be caused by neutron particles. The major contributions of this thesis are twofold. Firstly, in order to address Ultra-Low Power (ULP) design limitations, a novel driver scheme has been configured. This scheme uses a bootstrap circuitry which boosts the driver’s ability to drive a long interconnect with an important feedback feature in it. Hence, this approach achieves two objectives: improving performance and mitigating power consumption. Those achievements are essential in designing ULP circuits along with occupying a smaller footprint and being immune to noise, observed in this design as well. These have been verified by comparing the proposed design to the previous and traditional circuits using a simulation tool. Additionally, the boosting based approach has been shown beneficial in mitigating the effects of single event upset (SEU)s, which are known to affect DSM circuits working under low voltages. Secondly, the CMOS circuit driving a distributed RLC load has been brought in its analysis into the fractional order domain. This model will make the on-chip interconnect structure easy to adjust by including the effect of fractional orders on the interconnect timing, which has not been considered before. A second-order model for the transfer functions of the proposed general structure is derived, keeping the complexity associated with second-order models for this class of circuits at a minimum. The approach here attaches an important trait of robustness to the circuit design procedure; namely, by simply adjusting the fractional order we can avoid modifying the circuit components. This can also be used to optimise the estimation of the system’s delay for a broad range of frequencies, particularly at the beginning of the design flow, when computational speed is of paramount importance.Iraqi Ministry of Higher Education and Scientific Researc

Model Order Reduction

An increasing complexity of models used to predict real-world systems leads to the need for algorithms to replace complex models with far simpler ones, while preserving the accuracy of the predictions. This three-volume handbook covers methods as well as applications. This third volume focuses on applications in engineering, biomedical engineering, computational physics and computer science

Modeling and Design of Passive Planar Components for EMI Filters

Les composants magnétiques en technologie planar répondent aux exigences actuelles de l Electronique de Puissance (EP), à savoir la montée en fréquence de commutation des structures d EP et la réduction du volume des convertisseurs. La première tendance impose des contraintes fortes en termes de compatibilité électromagnétique (CEM) des équipements. Ces dernières doivent être prises en compte par les ingénieurs dès la phase conception des convertisseurs en se basant sur des modèles fiables, peu développés pour les composants planar dans la littérature scientifique. Ce travail de thèse porte ainsi sur la modélisation des composants planar pour applications aux filtres CEM. Différentes méthodes sont développées au cours de cette thèse pour arriver à évaluer de manière fine les éléments parasites des inductances planar de mode commun : capacités parasites et inductances de fuite. Une partie du travail a porté sur la modélisation par circuits équivalents du comportement fréquentiel des inductances de MC. Une approche automatisée, basée sur un algorithme de fitting a ainsi été développée pour élaborer des circuits équivalents fiables et robustes. Des approches analytiques (Décomposition du Champ Electrique) et semi-analytiques (Fonctions de Green) ont aussi été proposées pour évaluer les valeurs des éléments parasites. La dernière partie de la thèse est plus orientée conception, avec la réalisation de deux structures de composants innovantes, la première se basant sur une technique de compensation des capacités parasites à l aide d éléments parasites structuraux et la seconde sur l association de deux noyaux magnétiques, possédant matériaux et géométries différentesThe magnetic components with planar technology join in the current trends in Power Electronics (PE), namely increasing the switching frequency of PE structures and reducing the size of the power converters. The first tendency imposes strong constraints in terms of electromagnetic compatibility of equipments. The latter has to be considered by engineers at the beginning of the design of Power converters on the basis of reliable models, which are not sufficiently developed for planar components in scientific literature. This PhD work thereby focuses on the modeling of planar components for the applications of EMI filters. Different methods are developed during this study in order to accurately evaluate the parasitic elements of planar common-mode chokes: parasitic capacitances and leakage inductances. A part of this dissertation concerns the equivalent circuit modeling of the frequency behavior of CM chokes. An automated approach, based on a fitting algorithm developed for elaborating reliable and robust equivalent circuits. Analytical approaches (Electric Field Decomposition) and semi-analytical (Green s Function) are proposed as well for calculating the values of these parasitic elements. The last part of this dissertation is oriented to conception, with the realization of two structures of innovative components, the first one based on a parasitic capacitance cancellation technique using structural parasitic elements and the second one on the association of two magnetic cores with different materials and geometriesVILLENEUVE D'ASCQ-ECLI (590092307) / SudocSudocFranceF

Passivity compensation algorithm for method-of-characteristics-based multiconductor transmission line interconnect macromodels

Computation of passive and compact macromodels of distributed interconnects has gained considerable importance during the recent years. Method of characteristics (MoC) is widely used for macromodeling of transmission lines, however, it may not be guaranteed passive. This paper presents a new algorithm for passivity enforcement of MoC-based macromodels of multiconductor transmission lines. The algorithm is based on the first-order perturbation of the related delay differential equations and can handl