TSV Equivalent Circuit Model using 3D Full-Wave Analysis

This work presents a study to build lumped models for fault-free and faulty Through Silicon Vias (TSVs). Three dimensional full-wave simulations are performed to extract equivalent circuit models. The effects of parametric and catastrophic faults due to pin-holes, voids and open circuits on the equivalent circuit models have been determined through 3D simulations. The extracted TSV models are then used to conduct delay tests to determine the required measurement resolution to detect TSV defects. It is shown that the substrate conductivity has a considerable effect on TSV fault characterization. It is also shown that, regardless of the substrate type, even a relatively large void does not alter the TSV resistance or its parasitic capacitance noticeably at 1GHz solution frequency. An on-chip test solution for TSV parametric faults requires a dedicated high resolution measurement circuit due to the minor variations of TSV circuit model parameters

An On-chip PVT Resilient Short Time Measurement Technique

As the CMOS technology nodes continue to shrink, the challenges of developing manufacturing tests for integrated circuits become more difficult to address. To detect parametric faults of new generation of integrated circuits such as 3D ICs, on-chip short-time intervals have to be accurately measured. The accuracy of an on-chip time measurement module is heavily affected by Process, supply Voltage, and Temperature (PVT) variations. This work presents a new on-chip time measurement scheme where the undesired effects of PVT variations are attenuated significantly. To overcome the effects of PVT variations on short-time measurement, phase locking methodology is utilized to implement a robust Vernier delay line. A prototype Time-to-Digital Converter (TDC) has been fabricated using TSMC 0.180 µm CMOS technology and experimental measurements have been carried out to verify the performance parameters of the TDC. The measurement results indicate that the proposed solution reduces the effects of PVT variations by more than tenfold compared to a conventional on-chip TDC. A coarse-fine time interval measurement scheme which is resilient to the PVT variations is also proposed. In this approach, two Delay Locked Loops (DLLs) are utilized to minimize the effects of PVT on the measured time intervals. The proposed scheme has been implemented using CMOS 65nm technology. Simulation results using Advanced Design System (ADS) indicate that the measurement resolution varies by less than 0.1ps with ±15% variations of the supply voltage. The proposed method also presents a robust performance against process and temperature variations. The measurement accuracy changes by a maximum of 0.05ps from slow to fast corners. The implemented TDC presents a robust performance against temperature variations too and its measurement accuracy varies a few femto-seconds from -40 ºC to +100 ºC. The principle of robust short-time measurement was used in practice to design and implement a state-of-the-art Coordinate Measuring Machine (CMM) for an industry partner to measure geometrical features of transmission parts with micrometer resolution. The solution developed for the industry partner has resulted in a patent and a product in the market. The on-chip short-time measurement technology has also been utilized to develop a solution to detect Hardware Trojans

Nouvelle technique de test de type délai plus robuste à la variation d'impédance du réseau de distribution d'alimentation

De nos jours, le test de balayage à vitesse nominale (SBAST, Scan Based at-Speed Testing) est l’approche de test de type délai la plus dominante. Ce type de test vient avec certains inconvénients, comme le bruit de tension d’alimentation (PSN, Power Supply Noise) produit pendant le mode test, qui diffère de celui induit pendant le mode fonctionnel. Quelques techniques de test de type SBAST ont été développées pour réduire cette chute de tension. Mais un aspect particulier a été négligé dans la littérature, à savoir l’impact de la variation d’impédance du réseau de distribution d’alimentation (PDN, Power Delivery Network) sur les tests de type délai. Ce projet de maîtrise présente une nouvelle technique de test SBAST, nommée (OCAS, One Clock Alternated Shift) pour minimiser l’impact potentiel de la variation d’impédance du réseau de distribution d’alimentation. La stratégie derrière cette nouvelle technique est d’imiter autant que possible le signal d’horloge du mode fonctionnel. Le but de cette imitation est d’obtenir des conditions de distribution d’alimentation similaires à celle du mode fonctionnel pour protéger le circuit en mode test contre les variations de Vdd dues aux variations d’impédance. Comme cas d’étude, nous considérons la variation d’impédance du PDN qui peut se produire avec les circuits intégrés 3D avec la variation du nombre de puces du circuit sous test (CUT, Circuit Under Test). Les résultats des simulations HSPICE montrent que la technique OCAS est moins sensible à une telle variation d’impédance et qu’elle surpasse les principales techniques existantes de SBAST. De plus, les résultats de la couverture des pannes de transition de la technique OCAS obtenue avec les outils (ATPG, Automatic Test Pattern Generation) sont fort acceptables. Cependant, le nombre de vecteurs de test nécessaires pour y parvenir sont plus élevés, en raison des limitations de ces outils