Traffic classification and management based flow statistics netfpga

The internet bandwidth increased significantly over the past years but the problem of network bandwidth management remained a key issue. One of the major problems associated with bandwidth management is network bottleneck, which is the overcapacity of network traffic due to abnormal application bandwidth usage. With the release of new applications every year, especially P2P applications that require high bandwidth, effective network management has become even more important. Congestion can be caused inside a network by numerous flows and high bandwidth applications that may dominate the total bandwidth allocation, affecting normal users. This report presents an approach to detect and manage high bandwidth traffic flows in a congested network, providing fair bandwidth usage to normal users and restricting bandwidth-heavy applications. Flow statistics information is used for classification of network traffic by applying k-means clustering. An inline rate-limiter technique based on queue management is used for controlling high bandwidth flows. The proposed traffic shapping method queues the header packets of flows that are classified as high bandwidth flows. These modules are integrated into the NetFPGA platform, where decision making is carried out with minimal intervention of network administrators by only updating the classifier model when accuracy falls below a threshold line. It ensure zero intrusion of user privacy and at the same time it is able to reduce the high bandwidth rate, providing fair network usage for home users

A Modular Approach to Adaptive Reactive Streaming Systems

The latest generations of FPGA devices offer large resource counts that provide the headroom to implement large-scale and complex systems. However, there are increasing challenges for the designer, not just because of pure size and complexity, but also in harnessing effectively the flexibility and programmability of the FPGA. A central issue is the need to integrate modules from diverse sources to promote modular design and reuse. Further, the capability to perform dynamic partial reconfiguration (DPR) of FPGA devices means that implemented systems can be made reconfigurable, allowing components to be changed during operation. However, use of DPR typically requires low-level planning of the system implementation, adding to the design challenge. This dissertation presents ReShape: a high-level approach for designing systems by interconnecting modules, which gives a ‘plug and play’ look and feel to the designer, is supported by tools that carry out implementation and verification functions, and is carried through to support system reconfiguration during operation. The emphasis is on the inter-module connections and abstracting the communication patterns that are typical between modules – for example, the streaming of data that is common in many FPGA-based systems, or the reading and writing of data to and from memory modules. ShapeUp is also presented as the static precursor to ReShape. In both, the details of wiring and signaling are hidden from view, via metadata associated with individual modules. ReShape allows system reconfiguration at the module level, by supporting type checking of replacement modules and by managing the overall system implementation, via metadata associated with its FPGA floorplan. The methodology and tools have been implemented in a prototype for a broad domain-specific setting – networking systems – and have been validated on real telecommunications design projects

Parameterizable decision tree classifier on NETFPGA

Machine learning approaches based on decision trees (DTs) have been proposed for classifying networking traffic. Although this technique has been proven to have the ability to classify encrypted and unknown traffic, the software implementation of DT cannot cope with the current speed of packet traffic. In this paper, hardware architecture of decision tree is proposed on NetFPGA platform. The proposed architecture is fully parameterizable to cover wide range of applications. Several optimizations have been done on the DT structure to improve the tree search performance and to lower the hardware cost. The optimizations proposed are: a) node merging to reduce the computation latency, b) limit the number of nodes in the same level to control the memory usage, and c) support variable throughput to reduce the hardware cost of the tree