Custom optimization algorithms for efficient hardware implementation

The focus is on real-time optimal decision making with application in advanced control systems. These computationally intensive schemes, which involve the repeated solution of (convex) optimization problems within a sampling interval, require more efficient computational methods than currently available for extending their application to highly dynamical systems and setups with resource-constrained embedded computing platforms. A range of techniques are proposed to exploit synergies between digital hardware, numerical analysis and algorithm design. These techniques build on top of parameterisable hardware code generation tools that generate VHDL code describing custom computing architectures for interior-point methods and a range of first-order constrained optimization methods. Since memory limitations are often important in embedded implementations we develop a custom storage scheme for KKT matrices arising in interior-point methods for control, which reduces memory requirements significantly and prevents I/O bandwidth limitations from affecting the performance in our implementations. To take advantage of the trend towards parallel computing architectures and to exploit the special characteristics of our custom architectures we propose several high-level parallel optimal control schemes that can reduce computation time. A novel optimization formulation was devised for reducing the computational effort in solving certain problems independent of the computing platform used. In order to be able to solve optimization problems in fixed-point arithmetic, which is significantly more resource-efficient than floating-point, tailored linear algebra algorithms were developed for solving the linear systems that form the computational bottleneck in many optimization methods. These methods come with guarantees for reliable operation. We also provide finite-precision error analysis for fixed-point implementations of first-order methods that can be used to minimize the use of resources while meeting accuracy specifications. The suggested techniques are demonstrated on several practical examples, including a hardware-in-the-loop setup for optimization-based control of a large airliner.Open Acces

Uma avaliação experimental da plataforma parallella utilizando controle preditivo baseado em modelo como um estudo de caso

Dissertação (mestrado)—Universidade de Brasília, Faculdade de Tecnologia, Departamento de Engenharia Mecânica, 2017.Nas últimas décadas, o poder computacional de sistemas embarcados têm crescido de forma muito rápida. Em geral, tais sistema são projetados para operar sob restrições como portabilidade (peso e tamanho), consumo de recursos, baixo consumo de energia e dissipação de potência. Assim, motivado pelos fatores supracitados e pelo avanço tecnológico, assim como pela demanda crescente de desempenho por parte das aplicações embarcadas, têm surgido vários processadores e plataformas de hardware que fazem uso de arquiteturas multicore, com destaque para a Parallella, uma plataforma de alto desempenho e baixo consumo energético. Nesse sentido, o presente trabalho traz a proposta de se avaliar tal plataforma sob uma abordagem experimental, como foco em seu coprocessador Epiphany de 16 cores, quando utilizada como um acelerador em software para aplicações de controle preditivo baseado em modelo como um estudo de caso, devido sua relevância para o grupo de pesquisa do LEIA (Laboratório de Sistemas Embarcados e Aplicações de Circuitos Integrados – Universidade de Brasília). Os resultados mostram que, apesar de restrições críticas como o tamanho da memória local dos cores, a plataforma Parallella se apresenta como uma arquitetura em potencial, podendo ser vista como uma alternativa à aceleração de algoritmos em hardware. Melhorias futuras como a expansão do número de núcleos do MPSoC Epiphany e da memória local dos mesmos, como previsto pelos fundadores do projeto, poderão alavancar ainda mais o uso de tal arquitetura em aplicações embarcadas.In the last decades, the computational power of embedded systems has grown very fast. In general, such systems are designed to operate under constraints such as portability, resource consumption, low power consumption and power dissipation. Thus, due to the aforementioned factors and technological advances, as well as the increasing demand for performance by embedded applications, there have been several processors and hardware platforms that make use of multicore architectures, with emphasis on a Parallella, a platform of high performance and low consumption. In this sense, the present work presents a proposal to evaluate such platform in an experimental approach, focusing on its Epiphany 16-core co-processor, when used as a software accelerator for model-based predictive control applications as a case study, due to its relevance to the research group of LEIA (Laboratory of Embedded Systems and Applications of Integrated Circuits - University of Brasilia). The results show that, despite critical constraints such as the local memory size of the cores, a Parallella platform presents itself as a potential architecture and can be seen as an alternative to accelerating hardware algorithms. Future improvements such as the expansion of the number of MPSoC Epiphany cores and their local memory, as predicted by the founders of the project, can leverage the use of this architecture in embedded application