Bit-level pipelined digit-serial array processors

A new architecture for high performance digit-serial vector inner product (VIP) which can be pipelined to the bit-level is introduced. The design of the digit-serial vector inner product is based on a new systematic design methodology using radix-2n arithmetic. The proposed architecture allows a high level of bit-level pipelining to increase the throughput rate with minimum initial delay and minimum area. This will give designers greater flexibility in finding the best tradeoff between hardware cost and throughput rate. It is shown that sub-digit pipelined digit-serial structure can achieve a higher throughput rate with much less area consumption than an equivalent bit-parallel structure. A twin-pipe architecture to double the throughput rate of digit-serial multipliers and consequently that of the digit-serial vector inner product is also presented. The effect of the number of pipelining levels and the twin-pipe architecture on the throughput rate and hardware cost are discussed. A two's complement digit-serial architecture which can operate on both negative and positive numbers is also presented

An Electrically Programmable Split-Electrode Charge-Coupled Transversal Filter (EPSEF)

A CCD split-electrode transversal filter (EPSEF) with analog controlled tap weights is described. The programmable tap weighting utilizes a novel analog multiplier for sampled data, based on charge profiling underneath a resistive gate structure. The EPSEF device concept and the performance data of a prototype filter with eight programmable taps are presented. Applications of the EPSEF in several programmed filter functions and in an adaptive filter system are demonstrated

An Improved Variable Structure Adaptive Filter Design and Analysis for Acoustic Echo Cancellation

In this research an advance variable structure adaptive Multiple Sub-Filters (MSF) based algorithm for single channel Acoustic Echo Cancellation (AEC) is proposed and analyzed. This work suggests a new and improved direction to find the optimum tap-length of adaptive filter employed for AEC. The structure adaptation, supported by a tap-length based weight update approach helps the designed echo canceller to maintain a trade-off between the Mean Square Error (MSE) and time taken to attain the steady state MSE. The work done in this paper focuses on replacing the fixed length sub-filters in existing MSF based AEC algorithms which brings refinements in terms of convergence, steady state error and tracking over the single long filter, different error and common error algorithms. A dynamic structure selective coefficient update approach to reduce the structural and computational cost of adaptive design is discussed in context with the proposed algorithm. Simulated results reveal a comparative performance analysis over proposed variable structure multiple sub-filters designs and existing fixed tap-length sub-filters based acoustic echo cancellers