175 research outputs found
Generating reversible circuits from higher-order functional programs
Boolean reversible circuits are boolean circuits made of reversible
elementary gates. Despite their constrained form, they can simulate any boolean
function. The synthesis and validation of a reversible circuit simulating a
given function is a difficult problem. In 1973, Bennett proposed to generate
reversible circuits from traces of execution of Turing machines. In this paper,
we propose a novel presentation of this approach, adapted to higher-order
programs. Starting with a PCF-like language, we use a monadic representation of
the trace of execution to turn a regular boolean program into a
circuit-generating code. We show that a circuit traced out of a program
computes the same boolean function as the original program. This technique has
been successfully applied to generate large oracles with the quantum
programming language Quipper.Comment: 21 pages. A shorter preprint has been accepted for publication in the
Proceedings of Reversible Computation 2016. The final publication is
available at http://link.springer.co
Design and analysis of efficient QCA reversible adders
Quantum-dot cellular automata (QCA) as an emerging nanotechnology are envisioned to overcome the scaling and the heat dissipation issues of the current CMOS technology. In a QCA structure, information destruction plays an essential role in the overall heat dissipation, and in turn in the power consumption of the system. Therefore, reversible logic, which significantly controls the information flow of the system, is deemed suitable to achieve ultra-low-power structures. In order to benefit from the opportunities QCA and reversible logic provide, in this paper, we first review and implement prior reversible full-adder art in QCA. We then propose a novel reversible design based on three- and five-input majority gates, and a robust one-layer crossover scheme. The new full-adder significantly advances previous designs in terms of the optimization metrics, namely cell count, area, and delay. The proposed efficient full-adder is then used to design reversible ripple-carry adders (RCAs) with different sizes (i.e., 4, 8, and 16 bits). It is demonstrated that the new RCAs lead to 33% less garbage outputs, which can be essential in terms of lowering power consumption. This along with the achieved improvements in area, complexity, and delay introduces an ultra-efficient reversible QCA adder that can be beneficial in developing future computer arithmetic circuits and architecture
Low Power Reversible Parallel Binary Adder/Subtractor
In recent years, Reversible Logic is becoming more and more prominent
technology having its applications in Low Power CMOS, Quantum Computing,
Nanotechnology, and Optical Computing. Reversibility plays an important role
when energy efficient computations are considered. In this paper, Reversible
eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design
III are proposed. In all the three design approaches, the full Adder and
Subtractors are realized in a single unit as compared to only full Subtractor
in the existing design. The performance analysis is verified using number
reversible gates, Garbage input/outputs and Quantum Cost. It is observed that
Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is
efficient compared to Design I, Design II and existing design.Comment: 12 pages,VLSICS Journa
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