Limitations of PLL simulation: hidden oscillations in MatLab and SPICE

Nonlinear analysis of the phase-locked loop (PLL) based circuits is a challenging task, thus in modern engineering literature simplified mathematical models and simulation are widely used for their study. In this work the limitations of numerical approach is discussed and it is shown that, e.g. hidden oscillations may not be found by simulation. Corresponding examples in SPICE and MatLab, which may lead to wrong conclusions concerning the operability of PLL-based circuits, are presented

Comparative analysis between different approaches for single-phase PLLs

"In press"This paper presents a comparative analysis between two distinct synchronizing circuits, which are usually applied as the core of control algorithms for single-phase power quality applications. One of these synchronizing circuits corresponds to a single-phase Phase-Locked Loop (PLL), implemented in α-β coordinates (αβ-PLL), whereas the other one corresponds to the Enhanced PLL (E-PLL). The major contribution of this paper is to present a single-phase PLL oriented to power quality applications, with a very simple structure, capable to be synchronized with the fundamental component of an input signal (voltage or current), even considering substantial disturbances, such as, frequency deviations, phase shifts, harmonic components and amplitude variations. Simulation and experimental results, involving these two synchronizing circuits submitted to three different test cases, are provided in order to compare their transient and steady-state performance. Moreover, it is also presented a comparison involving the processing speed and memory requirements of these synchronizing circuits in the DSP TMS320F28335

Limitations of the classical phase-locked loop analysis

Nonlinear analysis of the classical phase-locked loop (PLL) is a challenging task. In classical engineering literature simplified mathematical models and simulation are widely used for its study. In this work the limitations of classical engineering phase-locked loop analysis are demonstrated, e.g., hidden oscillations, which can not be found by simulation, are discussed. It is shown that the use of simplified dynamical models and the application of simulation may lead to wrong conclusions concerning the operability of PLL-based circuits

Comparisons between synchronizing circuits to control algorithms for single-phase active converters

This paper presents a comparative analysis between synchronizing circuits applied to control algorithms for single-phase active converters. One of these synchronizing circuits corresponds to the single-phase PLL (Phase Locked Loop), implemented in α-β coordinates, whereas the other one corresponds to the E-PLL (Enhanced PLL). These synchronizing circuits are compared in several aspects as processing and settling time and memory space requirements. Moreover, the performance of a single-phase back-to-back converter is also presented, with its control algorithm based on these Synchronizing Circuits. Each one of the control algorithms were implemented in a DSP microprocessor TMS320F2812F from Texas Instruments. Simulation and experimental results, through a back-to-back converter prototype, are presented.Fundação para a Ciência e a Tecnologia (FCT

A Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and ±35 ps Jitter

A fully integrated phase-locked loop (PLL) fabricated in a 0.24μm, 2.5v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chips. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24μm CMOS technologies. Also it has very low peak-to-peak jitter less than ±35ps at 1.25GHz output frequency

A Low Noise Sub-Sampling PLL in Which Divider Noise Is Eliminated and PD-CP Noise Is not multiplied by N^2

This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP)that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by N2 in this sub-sampling PLL, resulting in a low noise contribution from the PD/CP. Moreover, no frequency divider is needed in the locked state and hence divider noise and power can be eliminated. An added frequency locked loop guarantees correct frequency locking without degenerating jitter performance when in lock. The PLL is implemented in a standard 0.18- m CMOS process. It consumes 4.2 mA from a 1.8 V supply and occupies an active area of 0.4 X 0.45 m