MESFET Optimization and Innovative Design for High Current Device Applications

abstract: There will always be a need for high current/voltage transistors. A transistor that has the ability to be both or either of these things is the silicon metal-silicon field effect transistor (MESFET). An additional perk that silicon MESFET transistors have is the ability to be integrated into the standard silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) process flow. This makes a silicon MESFET transistor a very valuable device for use in any standard CMOS circuit that may usually need a separate integrated circuit (IC) in order to switch power on or from a high current/voltage because it allows this function to be performed with a single chip thereby cutting costs. The ability for the MESFET to cost effectively satisfy the needs of this any many other high current/voltage device application markets is what drives the study of MESFET optimization. Silicon MESFETs that are integrated into standard SOI CMOS processes often receive dopings during fabrication that would not ideally be there in a process made exclusively for MESFETs. Since these remnants of SOI CMOS processing effect the operation of a MESFET device, their effect can be seen in the current-voltage characteristics of a measured MESFET device. Device simulations are done and compared to measured silicon MESFET data in order to deduce the cause and effect of many of these SOI CMOS remnants. MESFET devices can be made in both fully depleted (FD) and partially depleted (PD) SOI CMOS technologies. Device simulations are used to do a comparison of FD and PD MESFETs in order to show the advantages and disadvantages of MESFETs fabricated in different technologies. It is shown that PD MESFET have the highest current per area capability. Since the PD MESFET is shown to have the highest current capability, a layout optimization method to further increase the current per area capability of the PD silicon MESFET is presented, derived, and proven to a first order.Dissertation/ThesisM.S. Electrical Engineering 201

Perpendicular Reading of Single Confined Magnetic Skyrmions

Thin-film sub-5 nm magnetic skyrmions constitute an ultimate scaling alternative for future digital data storage. Skyrmions are robust non-collinear spin-textures that can be moved and manipulated by small electrical currents. We show here an innovative technique to detect isolated nanoskyrmions with a current-perpendicular-to-plane geometry, which has immediate implications for device concepts. We explore the physics behind such a mechanism by studying the atomistic electronic structure of the magnetic quasiparticles. We investigate how the isolated skyrmion local-density-of-states which tunnels into the vacuum, when compared to the ferromagnetic background, is modified by the site-dependent spin-mixing of electronic states with different relative canting angles. Local transport properties are sensitive to this effect, as we report an atomistic conductance anisotropy of over 20% for magnetic skyrmions in Pd/Fe/Ir(111) thin-films. In single skyrmions, engineering this spin-mixing magnetoresistance possibly could be incorporated in future magnetic storage technologies

Magnetic anisotropies of late transition metal atomic clusters

We analyze the impact of the magnetic anisotropy on the geometric structure and magnetic ordering of small atomic clusters of palladium, iridium, platinum and gold, using Density Functional Theory. Our results highlight the absolute need to include self-consistently the spin orbit interaction in any simulation of the magnetic properties of small atomic clusters, and a complete lack of universality in the magnetic anisotropy of small-sized atomic clusters.Comment: 4 pages, 5 figures, 1 EPAPS fil

Metal contacts to lowly doped Si and ultra thin SOI

We present our investigations on the fabrication of ohmic and Schottky contacts of several metals on lowly doped bulk Si and SOI wafers. Through this paper we evaluate the fabrication of rectifying devices in which no doping is intentionally introduced

Depletion isolation effect in Vertical MOSFETS during transition from partial to fully depleted operation

A simulation study is made of floating-body effects (FBEs) in vertical MOSFETs due to depletion isolation as the pillar thickness is reduced from 200 to 10 nm. For pillar thicknesses between 200–60 nm, the output characteristics with and without impact ionization are identical at a low drain bias and then diverge at a high drain bias. The critical drain bias Vdc for which the increased drain–current is observed is found to decrease with a reduction in pillar thickness. This is explained by the onset of FBEs at progressively lower values of the drain bias due to the merging of the drain depletion regions at the bottom of the pillar (depletion isolation). For pillar thicknesses between 60–10 nm, the output characteristics show the opposite behavior, namely, the critical drain bias increases with a reduction in pillar thickness. This is explained by a reduction in the severity of the FBEs due to the drain debiasing effect caused by the elevated body potential. Both depletion isolation and gate–gate coupling contribute to the drain–current for pillar thicknesses between 100–40 nm

Evidence of Spin-Filtering in Quantum Constrictions with Spin-Orbit Interaction

A new type of blockade effect - spin-orbit blockade (SOB) - is found in the conduction of a quantum dot (QD) made of a material with spin-orbit interaction. The blockade arises from spin-filtering effect in a quantum point contact (QPC), which is a component of the QD. Hence the appearance of the blockade itself evidences the spin-filtering effect in the QPC. The lower bound of filtering efficiency is estimated to be above 80%.Comment: 4 pages, 4 figure