LEGaTO: first steps towards energy-efficient toolset for heterogeneous computing

LEGaTO is a three-year EU H2020 project which started in December 2017. The LEGaTO project will leverage task-based programming models to provide a software ecosystem for Made-in-Europe heterogeneous hardware composed of CPUs, GPUs, FPGAs and dataflow engines. The aim is to attain one order of magnitude energy savings from the edge to the converged cloud/HPC.Peer ReviewedPostprint (author's final draft

NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors

© 2016 Cheung, Schultz and Luk.NeuroFlow is a scalable spiking neural network simulation platform for off-the-shelf high performance computing systems using customizable hardware processors such as Field-Programmable Gate Arrays (FPGAs). Unlike multi-core processors and application-specific integrated circuits, the processor architecture of NeuroFlow can be redesigned and reconfigured to suit a particular simulation to deliver optimized performance, such as the degree of parallelism to employ. The compilation process supports using PyNN, a simulator-independent neural network description language, to configure the processor. NeuroFlow supports a number of commonly used current or conductance based neuronal models such as integrate-and-fire and Izhikevich models, and the spike-timing-dependent plasticity (STDP) rule for learning. A 6-FPGA system can simulate a network of up to ~600,000 neurons and can achieve a real-time performance of 400,000 neurons. Using one FPGA, NeuroFlow delivers a speedup of up to 33.6 times the speed of an 8-core processor, or 2.83 times the speed of GPU-based platforms. With high flexibility and throughput, NeuroFlow provides a viable environment for large-scale neural network simulation

Optimal Modeled Six-Phase Space Vector Pulse Width Modulation Method for Stator Voltage Harmonic Suppression

Dual Y shift 30 six-phase motors are expected to be extensively applied in high-power yet energy-effective fields, and a harmonic-suppressing control strategy plays a vital role in extending their prominent features of low losses and ultra-quiet operation. Aiming at the suppression of harmonic voltages, this paper proposes a six-phase space vector pulse width modulation method based on an optimization model, namely OM-SVPWM. First, four adjacent large vectors are employed in each of 12 sectors on a fundamental sub-plane. Second, the optimization model is constructed to intelligently determine activation durations of the four vectors, where its objective function aims to minimize the synthesis result on a harmonic sub-plane, and its constraint condition is that the synthesis result on the fundamental sub-plane satisfies a reference vector. Finally, to meet the real-time requirement, optimum solutions are obtained by using general central path following algorithm (GCPFA). Simulation and experiment results prove that, the OM-SVPWM performs around 37% better than a state-of-the-art competitive SVPWM in terms of harmonics suppression, which promise the proposed OM-SVPWM conforms to the energy-effective direction in actual engineering applications.Peer reviewe

OPTIMIZING LARGE COMBINATIONAL NETWORKS FOR K-LUT BASED FPGA MAPPING

Optimizing by partitioning is a central problem in VLSI design automation, addressing circuit’s manufacturability. Circuit partitioning has multiple applications in VLSI design. One of the most common is that of dividing combinational circuits (usually large ones) that will not fit on a single package among a number of packages. Partitioning is of practical importance for k-LUT based FPGA circuit implementation. In this work is presented multilevel a multi-resource partitioning algorithm for partitioning large combinational circuits in order to efficiently use existing and commercially available FPGAs packagestwo-way partitioning, multi-way partitioning, recursive partitioning, flat partitioning, critical path, cutting cones, bottom-up clusters, top-down min-cut